On Tue, Oct 16, 2012 at 11:28 PM, Aurelien Jarno <[email protected]> wrote: > Like the MOVr instruction, the FMOVr instruction has the condition > encoded between bits 10 and 12.
Thanks, applied. > > Cc: Blue Swirl <[email protected]> > Signed-off-by: Aurelien Jarno <[email protected]> > --- > target-sparc/translate.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target-sparc/translate.c b/target-sparc/translate.c > index 6cef96b..6d05e7d 100644 > --- a/target-sparc/translate.c > +++ b/target-sparc/translate.c > @@ -3154,7 +3154,7 @@ static void disas_sparc_insn(DisasContext * dc, > unsigned int insn) > #define FMOVR(sz) \ > do { \ > DisasCompare cmp; \ > - cond = GET_FIELD_SP(insn, 14, 17); \ > + cond = GET_FIELD_SP(insn, 10, 12); \ > cpu_src1 = get_src1(insn, cpu_src1); \ > gen_compare_reg(&cmp, cond, cpu_src1); \ > gen_fmov##sz(dc, &cmp, rd, rs2); \ > -- > 1.7.10.4 >
