Usual target-arm pullreq. This one has a couple of bugfixes for
issues in the cp15 rework, and the LPAE patch series (including
switching to 64 bit physaddrs for ARM, and a trivial imx_avic
patch which is needed as a prerequisite for that).
thanks
-- PMM
The following changes since commit 92336855975805d88c7979f53bc05c2d47abab04:
megasas: disable due to build breakage (2012-07-09 18:16:16 -0500)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
Paul Brook (1):
target-arm: Fix CP15 based WFI
Peter Maydell (14):
target-arm: Fix typo that meant TTBR1 accesses went to TTBR0
target-arm: Fix some copy-and-paste errors in cp register names
target-arm: Fix TCG temp handling in 64 bit cp writes
hw/imx_avic.c: Avoid format error when target_phys_addr_t is 64 bits
ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits
target-arm: Implement privileged-execute-never (PXN)
target-arm: Extend feature flags to 64 bits
target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers
target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE
target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE
target-arm: Use target_phys_addr_t in get_phys_addr()
target-arm: Implement long-descriptor PAR format
target-arm: Implement TTBCR changes for LPAE
target-arm: Add support for long format translation table walks
configure | 2 +-
hw/imx_avic.c | 2 +-
target-arm/cpu.c | 6 +-
target-arm/cpu.h | 15 +-
target-arm/helper.c | 441 +++++++++++++++++++++++++++++++++++++++++++-----
target-arm/machine.c | 10 +-
target-arm/translate.c | 4 +-
7 files changed, 428 insertions(+), 52 deletions(-)
