Re: [PATCH] hw/net/xilinx_axienet.c: Prevent writes to PHY Identification registers

[Philippe Mathieu-Daudé]

On 5/3/26 13:13, Jim MacArthur wrote:

There are other registers in the PHY model which should be partially or
entirely read-only, but this solves the immediate issue.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3297

Signed-off-by: Jim MacArthur <jim.macart...@linaro.org>
---

diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index d85f8bb23f..970732b162 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -141,6 +141,10 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int 
data)
      regnum = req & 0x1f;
      DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
      switch (regnum) {
+        case 2:
+        case 3:
+            /* Writes to PHY Identification registers are disallowed */
+            break;
          default:
              phy->regs[regnum] = data;
              break;

Checkpatch.pl complains for pre-existing coding style:

ERROR: switch and case should be at the same indent
#27: FILE: hw/net/xilinx_axienet.c:143:
     switch (regnum) {
+        case 2:
+        case 3:

total: 1 errors, 0 warnings, 10 lines checked

Anyway, queued, thanks!