Hi,
On 2/20/26 11:11, Alireza Sanaee wrote:
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=max. It introduces three levels of caches and modifies
the cache description registers accordingly.
Reviewed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Alireza Sanaee <[email protected]>
---
target/arm/tcg/cpu64.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index fa80e48d2b..6a79ca9d43 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1167,6 +1167,16 @@ void aarch64_max_tcg_initfn(Object *obj)
uint64_t t;
uint32_t u;
+ SET_IDREG(isar, CLIDR, 0x8200123);
+ /* 64KB L1 dcache */
+ cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7);
+ /* 64KB L1 icache */
+ cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2);
+ /* 1MB L2 unified cache */
+ cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7);
+ /* 2MB L3 unified cache */
+ cpu->ccsidr[4] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7);
+
/*
* Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default
* to because we started with aarch64_a57_initfn(). A 'max' CPU might
Reviewed-by: Gustavo Romero <[email protected]>
Cheers,
Gustavo
