On 2/6/26 02:59, Anton Johansson wrote:
On 14/01/26, Anton Johansson wrote:
On 12/01/26, Philippe Mathieu-Daudé wrote:
On 12/1/26 13:22, Anton Johansson wrote:
When converting virtual to physical addresses,
TARGET_PHYS_ADDR_SPACE_BITS is used under PA-RISC 2.0, and an explicit
cast to uint32_t is used under PA-RISC 1.X.  Replace the former with a
more specific macro limited to mem_helper.c, and make the latter
conversion explicit by defining the size of the physical address space
for PA-RISC 1.X.

Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Anton Johansson <[email protected]>
---
   target/hppa/mem_helper.c | 23 ++++++++++++++++++-----
   1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index cce82e6599..8563bb0e2a 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -29,6 +29,19 @@
   #include "hw/core/cpu.h"
   #include "trace.h"
+/*
+ * 64-bit (PA-RISC 2.0) machines are assumed to run PA-8700, and 32-bit
+ * machines 7300LC.  This gives 44 and 32 bits of physical address space
+ * respectively.
+ *
+ *   CPU model        Physical address space bits
+ *   PA-7000--7300LC  32
+ *   PA-8000--8600    40
+ *   PA-8700--8900    44
+ */
+#define HPPA_PHYS_ADDR_SPACE_BITS_PA20 44
+#define HPPA_PHYS_ADDR_SPACE_BITS_PA1X 32
+
   hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr)
   {
       /*
@@ -42,8 +55,8 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr)
        * Since the supported physical address space is below 54 bits, the
        * H-8 algorithm is moot and all that is left is to truncate.
        */
-    QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 54);
-    return sextract64(addr, 0, TARGET_PHYS_ADDR_SPACE_BITS);
+    QEMU_BUILD_BUG_ON(HPPA_PHYS_ADDR_SPACE_BITS_PA20 > 54);
+    return sextract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20);
   }
   hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr)
@@ -67,7 +80,7 @@ hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr)
            * is what can be seen on physical machines too.
            */
           addr = (uint32_t)addr;
-        addr |= -1ull << (TARGET_PHYS_ADDR_SPACE_BITS - 4);
+        addr |= -1ull << (HPPA_PHYS_ADDR_SPACE_BITS_PA20 - 4);
       }
       return addr;
   }
@@ -217,7 +230,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr 
addr, int mmu_idx,
               if (hppa_is_pa20(env)) {
                   phys = hppa_abs_to_phys_pa2_w0(addr);
               } else {
-                phys = (uint32_t)addr;
+                phys = extract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA1X);
               }
               break;
           default:
@@ -558,7 +571,7 @@ static void itlbt_pa20(CPUHPPAState *env, target_ulong r1,
       /* Align per the page size. */
       ent->pa &= TARGET_PAGE_MASK << mask_shift;
       /* Ignore the bits beyond physical address space. */
-    ent->pa = sextract64(ent->pa, 0, TARGET_PHYS_ADDR_SPACE_BITS);
+    ent->pa = sextract64(ent->pa, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20);
       ent->t = extract64(r2, 61, 1);
       ent->d = extract64(r2, 60, 1);


Patch LGTM but fails on CI on 2 distinct jobs...

166/793 func-quick+func-hppa - qemu:func-hppa-seabios          TIMEOUT
90.05s   killed by signal 15 SIGTERM

209/276 qemu:func-quick+func-hppa / func-hppa-seabios
TIMEOUT         180.04s   (exit status 143 or signal 15 SIGTERM)

Works with:

-- >8 --
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 40d28435aa8..e7a26398c5a 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -82,3 +82,3 @@ hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr)
          addr = (uint32_t)addr;
-        addr |= -1ull << (TARGET_PHYS_ADDR_SPACE_BITS - 4);
+        addr |= -1ull << (HPPA_PHYS_ADDR_SPACE_BITS_PA20 - 8);
      }
---

PA-8000--8600 case with 40 bits?

Ouch!

AFAICT SeaBIOS runs on a C3700 (PA-8700) which is supposed to have a
44-bit physical address space.  I've tried to look around for any other
assumption of 40-bit physical addresses in QEMU and SeaBIOS but not
found anything yet..

Gave this another go, from what I can tell SeaBIOS uses 40-bit physical
addresses, see here for the firmware start and end addresses

   
https://github.com/hdeller/seabios-hppa/blob/master/src/parisc/hppa_hardware.h#L9
   
https://github.com/hdeller/seabios-hppa/blob/master/src/parisc/pafirmware.lds.S#L15

taking firmware start as an example, with the 44-bit physical address
space we map the 32-bit absolute address 0xf0000000 to the physical
address 0xf00f0000000, instead of 0xf0f0000000 which is the start address
in the SeaBIOS image.  Searching for f0f0* more 40-bit PDC address can
be found.  So I guess the test should run on a PA-8000--8600 machine
like C3600 instead..

I'll revert to using 40 bits for the physical address, and add a
comment since I'm not sure if there are other discrepencies between
C3600/3700 lurking.

Anton, thanks for looking into it!
I plan to add support for PA8700-PA8900 CPUs as well.
The new A400 machine support in my SeaBIOS "devel-v22" branch is the beginning
to support 64-bit only (PAT) machines with PA8800/PA8900 CPUs.

I wonder if it's somehow possible to support both 40 and 44 bits in a easy way?
E.g. adjusting SeaBIOS and qemu and always utilize 44 bits for the 64-bit CPUs?

Helge

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