Re: [PATCH v2] target/riscv: fix require_rvv passing on non-RVV CPUs

[Max Chou]

On 2026-02-05 13:52, Sébastien Michelland wrote:
> @@ -153,7 +153,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)
>  
>  #ifdef CONFIG_USER_ONLY
>      fs = EXT_STATUS_DIRTY;
> -    vs = EXT_STATUS_DIRTY;
> +    vs = riscv_has_ext(env, RVV) ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED;
>  #else
>      flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);

Hi Sébastien,

This v2 is good, but there’s a potential bug when users enable embedded
vector extensions (e.g., ZveXX) that aren’t standard RVV.

I suggest that we replace the RVV check with a check on the Zve32x,
which will be implied by all embedded vector extensions and standard
RVV.

    vs = cpu->cfg.ext_zve32x ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED;

rnax