On Wed, Feb 04, 2026 at 11:12:02AM +0000, Jonathan Cameron wrote: > On Tue, 3 Feb 2026 15:39:22 -0500 > "Michael S. Tsirkin" <[email protected]> wrote: > > > On Fri, Jan 09, 2026 at 02:45:04PM +0000, Jonathan Cameron wrote: > > > Lightly reworked version of Davidlohr's v4. > > > https://lore.kernel.org/qemu-devel/[email protected]/ > > > > > > Whilst I have several other series posted for merge this applies fine > > > to upstream, so no dependencies. > > > Davidlohr, please check I didn't mess anthing up and perhaps give tags > > > for the 3 new patches. > > > > applying this on top does seem to conflict. > > let me get rest merged then this can be rebased. > Hi Michael > > So I assume this is your v01-04-02-2026 branch. > > I tried rebasing on that and ran into some issue. > > Looks like you have a stale version of > [PATCH qemu v4 0/5] cxl: r3.2 specification event updates. > https://lore.kernel.org/all/[email protected]/ > > Markus had some comments that needed a new version. > Mostly updating a few more version numbers in the comments to keep things > consistent.
Right and *that* now has review comments so it looks like there will be v5 ... > > Not sure that has anything to do with the merge conflict. > > > > > v5 changes: > > > - Rebase much earlier in the CXL queue as Davidlohr had it beind some > > > stuff > > > I was carrying that is not ready for upstream just yet. > > > - Update the CFMWS flags directly as the patch doing restriction control > > > needs > > > some more thought. > > > - Bios tables test data updates. > > > - Don't provide flit mode control for gen_pcie_root_port as we don't need > > > it > > > for the rest of the series which is all about CXL. > > > > > > The following allows support for component basic back invalidation > > > discovery > > > and config, by exposing the BI routing table and decoder registers. > > > Instead > > > of going the type2[0] route, this series proposes adding support for type3 > > > hdm-db, which allows a more direct way of supporting BI in qemu. > > > > > > As BI is a dependent on the larger flits introduced in PCIe (and CXL 3.0) > > > add support for enabling that for CXL components. Negotiation is handled > > > via an equivalent of what we do for link speed. > > > > > > Davidlohr Bueso (3): > > > hw/pcie: Support enabling flit mode > > > hw/cxl: Support type3 HDM-DB > > > hw/cxl: Remove register special_ops->read() > > > > > > Ira Weiny (1): > > > hw/cxl: Refactor component register initialization > > > > > > Jonathan Cameron (3): > > > tests/bios-tables-test: Excluded CEDT.cxl for BI restriction > > > relaxation. > > > hw/cxl: Update CXL Fixed Memory Window ACPI description to include > > > Back Invalidate support. > > > tests/acpi/cxl: Update CEDT.cxl to allow BI in CFWMS > > > > > > docs/system/devices/cxl.rst | 23 +++ > > > include/hw/cxl/cxl_component.h | 87 +++++++-- > > > include/hw/cxl/cxl_device.h | 4 + > > > include/hw/pci-bridge/cxl_upstream_port.h | 1 + > > > include/hw/pci/pcie.h | 2 +- > > > include/hw/pci/pcie_port.h | 1 + > > > hw/acpi/cxl.c | 2 +- > > > hw/cxl/cxl-component-utils.c | 211 ++++++++++++++++------ > > > hw/mem/cxl_type3.c | 15 +- > > > hw/pci-bridge/cxl_downstream.c | 10 +- > > > hw/pci-bridge/cxl_root_port.c | 11 +- > > > hw/pci-bridge/cxl_upstream.c | 18 +- > > > hw/pci-bridge/pci_expander_bridge.c | 2 +- > > > hw/pci/pcie.c | 23 ++- > > > tests/data/acpi/x86/q35/CEDT.cxl | Bin 184 -> 184 bytes > > > 15 files changed, 313 insertions(+), 97 deletions(-) > > > > > > -- > > > 2.48.1 > > > > > >
