From: CLEMENT MATHIEU--DRIF <[email protected]>
Signed-off-by: Clement Mathieu--Drif <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
Message-Id: <[email protected]>
---
hw/i386/intel_iommu.c | 45 ++++++++++++++++++++++++----------
hw/i386/intel_iommu_internal.h | 6 ++++-
include/hw/i386/intel_iommu.h | 1 +
3 files changed, 38 insertions(+), 14 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 77adeed0cc..dd00079a40 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2862,8 +2862,10 @@ static bool vtd_inv_desc_reserved_check(IntelIOMMUState
*s,
static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
{
- uint64_t mask[4] = {VTD_INV_DESC_WAIT_RSVD_LO, VTD_INV_DESC_WAIT_RSVD_HI,
- VTD_INV_DESC_ALL_ONE, VTD_INV_DESC_ALL_ONE};
+ uint64_t mask[4] = {
+ VTD_INV_DESC_WAIT_RSVD_LO(s->ecap), VTD_INV_DESC_WAIT_RSVD_HI,
+ VTD_INV_DESC_ALL_ONE, VTD_INV_DESC_ALL_ONE
+ };
bool ret = true;
if (!vtd_inv_desc_reserved_check(s, inv_desc, mask, false,
@@ -4186,6 +4188,7 @@ static const Property vtd_properties[] = {
DEFINE_PROP_BOOL("x-flts", IntelIOMMUState, fsts, FALSE),
DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, false),
DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false),
+ DEFINE_PROP_BOOL("svm", IntelIOMMUState, svm, false),
DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
DEFINE_PROP_BOOL("stale-tm", IntelIOMMUState, stale_tm, false),
DEFINE_PROP_BOOL("fs1gp", IntelIOMMUState, fs1gp, true),
@@ -5096,6 +5099,10 @@ static void vtd_init(IntelIOMMUState *s)
vtd_spte_rsvd_large[3] &= ~VTD_SPTE_SNP;
}
+ if (s->svm) {
+ s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS;
+ }
+
vtd_reset_caches(s);
/* Define registers with default values and bit semantics */
@@ -5573,6 +5580,29 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error
**errp)
return false;
}
+ if (s->svm) {
+ if (!x86_iommu->dt_supported) {
+ error_setg(errp, "Need to set device IOTLB for svm");
+ return false;
+ }
+
+ if (!s->fsts) {
+ error_setg(errp, "Need to set flts for svm");
+ return false;
+ }
+
+ if (!x86_iommu->dma_translation) {
+ error_setg(errp, "Need to set dma-translation for svm");
+ return false;
+ }
+
+ if (!s->pasid) {
+ error_setg(errp, "Need to set PASID support for svm");
+ return false;
+ }
+ }
+
+
return true;
}
@@ -5583,17 +5613,6 @@ static void vtd_realize(DeviceState *dev, Error **errp)
X86MachineState *x86ms = X86_MACHINE(ms);
PCIBus *bus = pcms->pcibus;
IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
- X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
-
- if (s->pasid && x86_iommu->dt_supported) {
- /*
- * PASID-based-Device-TLB Invalidate Descriptor is not
- * implemented and it requires support from vhost layer which
- * needs to be implemented in the future.
- */
- error_setg(errp, "PASID based device IOTLB is not supported");
- return;
- }
if (!vtd_decide_config(s, errp)) {
return;
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 18d50191d2..11a53aa369 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -194,8 +194,10 @@
#define VTD_ECAP_PRS (1ULL << 29)
#define VTD_ECAP_MHMV (15ULL << 20)
#define VTD_ECAP_SRS (1ULL << 31)
+#define VTD_ECAP_NWFS (1ULL << 33)
#define VTD_ECAP_PSS (7ULL << 35) /* limit: MemTxAttrs::pid */
#define VTD_ECAP_PASID (1ULL << 40)
+#define VTD_ECAP_PDS (1ULL << 42)
#define VTD_ECAP_SMTS (1ULL << 43)
#define VTD_ECAP_SSTS (1ULL << 46)
#define VTD_ECAP_FSTS (1ULL << 47)
@@ -417,7 +419,9 @@ typedef union VTDPRDesc VTDPRDesc;
#define VTD_INV_DESC_WAIT_IF (1ULL << 4)
#define VTD_INV_DESC_WAIT_FN (1ULL << 6)
#define VTD_INV_DESC_WAIT_DATA_SHIFT 32
-#define VTD_INV_DESC_WAIT_RSVD_LO 0Xfffff180ULL
+#define VTD_INV_DESC_WAIT_RSVD_LO(ecap) (0Xfffff100ULL | \
+ (((ecap) & VTD_ECAP_PDS) \
+ ? 0 : (1 << 7)))
#define VTD_INV_DESC_WAIT_RSVD_HI 3ULL
/* Masks for Context-cache Invalidation Descriptor */
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index 6c61fd39c7..d600e5495f 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -275,6 +275,7 @@ struct IntelIOMMUState {
bool scalable_mode; /* RO - is Scalable Mode supported? */
bool fsts; /* RO - is first stage translation
supported? */
bool snoop_control; /* RO - is SNP filed supported? */
+ bool svm; /* RO - is SVA/SVM supported? */
dma_addr_t root; /* Current root table pointer */
bool root_scalable; /* Type of root table (scalable or not) */
--
MST
