v6: - Initialize a variable that causing a false warning with some versions of gcc. - Rebase. - Tag from Davidlohr for the ACPI change.
Based on - due to fuzz + context changes. 1. [PATCH qemu v4 0/5] cxl: r3.2 specification event updates. https://lore.kernel.org/qemu-devel/[email protected]/ 2. [PATCH qemu for 10.2 0/3] cxl: Additional RAS features support. https://lore.kernel.org/qemu-devel/[email protected]/ 3. [PATCH qemu 0/2] hw/cxl: Two media operations related fixes. https://lore.kernel.org/qemu-devel/[email protected]/ (most likely will apply fine with out this one) v5 changes: - Rebase much earlier in the CXL queue as Davidlohr had it beind some stuff I was carrying that is not ready for upstream just yet. - Update the CFMWS flags directly as the patch doing restriction control needs some more thought. - Bios tables test data updates. - Don't provide flit mode control for gen_pcie_root_port as we don't need it for the rest of the series which is all about CXL. The following allows support for component basic back invalidation discovery and config, by exposing the BI routing table and decoder registers. Instead of going the type2[0] route, this series proposes adding support for type3 hdm-db, which allows a more direct way of supporting BI in qemu. As BI is a dependent on the larger flits introduced in PCIe (and CXL 3.0) add support for enabling that for CXL components. Negotiation is handled via an equivalent of what we do for link speed. Davidlohr Bueso (3): hw/pcie: Support enabling flit mode hw/cxl: Support type3 HDM-DB hw/cxl: Remove register special_ops->read() Ira Weiny (1): hw/cxl: Refactor component register initialization Jonathan Cameron (3): tests/bios-tables-test: Excluded CEDT.cxl for BI restriction relaxation. hw/cxl: Update CXL Fixed Memory Window ACPI description to include Back Invalidate support. tests/acpi/cxl: Update CEDT.cxl to allow BI in CFWMS docs/system/devices/cxl.rst | 23 +++ include/hw/cxl/cxl_component.h | 87 +++++++-- include/hw/cxl/cxl_device.h | 4 + include/hw/pci-bridge/cxl_upstream_port.h | 1 + include/hw/pci/pcie.h | 2 +- include/hw/pci/pcie_port.h | 1 + hw/acpi/cxl.c | 2 +- hw/cxl/cxl-component-utils.c | 211 ++++++++++++++++------ hw/mem/cxl_type3.c | 15 +- hw/pci-bridge/cxl_downstream.c | 10 +- hw/pci-bridge/cxl_root_port.c | 11 +- hw/pci-bridge/cxl_upstream.c | 18 +- hw/pci-bridge/pci_expander_bridge.c | 2 +- hw/pci/pcie.c | 23 ++- tests/data/acpi/x86/q35/CEDT.cxl | Bin 184 -> 184 bytes 15 files changed, 313 insertions(+), 97 deletions(-) -- 2.51.0
