On 2/2/26 22:43, Philippe Mathieu-Daudé wrote:
In preparation of removing the cpu_ldl_code() and cpu_ldq_code()
wrappers, inline them.
Since RISC-V instructions are always stored in little-endian order
(see "Volume I: RISC-V Unprivileged ISA" document, chapter
'Instruction Encoding Spaces and Prefixes': "instruction fetch
in RISC-V is little-endian"), replace MO_TE -> MO_LE.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
---
target/riscv/translate.c | 3 ++-
target/riscv/zce_helper.c | 8 ++++++--
2 files changed, 8 insertions(+), 3 deletions(-)
Patch queued, thanks.
