Since RISC-V wgChecker [1] could permit the access in RO/WO permission, the IOMMUMemoryRegion could return different section for read & write access. To support this kind of IOMMUMemoryRegion in the path of CPU access, address_space_translate*() should also translate access_type to iommu_flags abd pass to IOMMUMemoryRegion. Thus, IOMMUMemoryRegion can return the correct section of specified access_type.
This patch is based on "[PATCH v2 0/3] Fix iotlb_to_section() for different AddressSpace.". Both RISC-V wgChecker [1] and RISC-V IOPMP [2] devices require this feature. [1] RISC-V WG: https://patchew.org/QEMU/[email protected]/ [2] RISC-V IOPMP: https://patchew.org/QEMU/[email protected]/ Based-on: <[email protected]> Jim Shu (2): accel/tcg: Pass access_type as an argument of tlb_set_page*() accel/tcg: address_space_translate*() will pass the correct iommu_flags accel/tcg/cputlb.c | 17 ++++++++++------- include/accel/tcg/iommu.h | 3 ++- include/exec/cputlb.h | 11 +++++++---- system/physmem.c | 16 +++++++++++----- target/alpha/helper.c | 2 +- target/avr/helper.c | 2 +- target/hppa/mem_helper.c | 1 - target/i386/tcg/system/excp_helper.c | 3 ++- target/loongarch/tcg/tlb_helper.c | 2 +- target/m68k/helper.c | 10 +++++++--- target/microblaze/helper.c | 8 ++++---- target/mips/tcg/system/tlb_helper.c | 4 ++-- target/openrisc/mmu.c | 2 +- target/ppc/mmu_helper.c | 2 +- target/riscv/cpu_helper.c | 2 +- target/rx/cpu.c | 3 ++- target/s390x/tcg/excp_helper.c | 2 +- target/sh4/helper.c | 2 +- target/sparc/mmu_helper.c | 6 +++--- target/tricore/helper.c | 2 +- target/xtensa/helper.c | 3 ++- 21 files changed, 61 insertions(+), 42 deletions(-) -- 2.43.0
