>>
>> +static void ati_host_data_reset(ATIHostDataState *hd)
>> +{
>> + hd->next = 0;
>> + hd->row = 0;
>> + hd->col = 0;
>> +}
>
> I wonder where the real chip keeps track of these. Isn't this where the
> dst_x dst_y would be updated? Or it may have some internal state not
> exposed as registers? Maybe if you can dump registers you could compare
> their values during blits after each host data reg write and check how
> they change to reveal if any of them are updated? (But only if you're
> curious; it would do for emulation using this approach with a separate
> state as well.)
>
So far it's looking to me like this is internal state not exposed
through the registers. I do see one register that increments after every
host_data* write but it's in the PM4/CCE range (0x07e8) and is completely
undocumented. It _is_ a bit surprising to see changes in that range given CCE
is disabled. But nothing really obvious or conclusive yet, unfortunately.
