The vfncvtbf16.sat.f.f.w instruction converts a vector of 16-bit floating-point numbers to a vector of 8-bit floating-point numbers with saturation. The VTYPE.altfmt field is used to select the format of the 8-bit floating-point numbers. * altfmt = 0: BF16 to OFP8.e4m3 * altfmt = 1: BF16 to OFP8.e5m2
Signed-off-by: Max Chou <[email protected]> --- target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvofp8.c.inc | 43 ++++++++++++++++++++++ target/riscv/translate.c | 1 + 3 files changed, 47 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvofp8.c.inc diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6e35c4b1e6..49201c0c20 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -973,6 +973,9 @@ vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm +# *** Zvfofp8min Extension *** +vfncvtbf16_sat_f_f_w 010010 . ..... 11111 001 ..... 1010111 @r2_vm + # *** Zvbc vector crypto extension *** vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvofp8.c.inc b/target/riscv/insn_trans/trans_rvofp8.c.inc new file mode 100644 index 0000000000..f1a7b0affd --- /dev/null +++ b/target/riscv/insn_trans/trans_rvofp8.c.inc @@ -0,0 +1,43 @@ +/* + * RISC-V translation routines for the OFP8 Standard Extensions. + * + * Copyright (C) 2025 SiFive, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#define REQUIRE_ZVFOFP8MIN(ctx) do { \ + if (!ctx->cfg_ptr->ext_zvfofp8min) { \ + return false; \ + } \ +} while (0) + + +static bool trans_vfncvtbf16_sat_f_f_w(DisasContext *ctx, arg_rmr *a) +{ + REQUIRE_FPU; + REQUIRE_ZVFOFP8MIN(ctx); + + if (opfv_narrow_check(ctx, a) && ctx->sew == MO_8) { + gen_helper_gvec_3_ptr *fn; + uint32_t data = 0; + + fn = ctx->altfmt ? gen_helper_vfncvtbf16_sat_f_f_w_ofp8e5m2 : + gen_helper_vfncvtbf16_sat_f_f_w_ofp8e4m3; + + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); + + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul); + data = FIELD_DP32(data, VDATA, VTA, ctx->vta); + data = FIELD_DP32(data, VDATA, VMA, ctx->vma); + tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), + vreg_ofs(ctx, a->rs2), tcg_env, + ctx->cfg_ptr->vlenb, + ctx->cfg_ptr->vlenb, data, fn); + finalize_rvv_inst(ctx); + return true; + } + return false; +} + diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a1c4b325e5..137022d7fb 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1219,6 +1219,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_rvbf16.c.inc" +#include "insn_trans/trans_rvofp8.c.inc" #include "decode-xthead.c.inc" #include "decode-xmips.c.inc" #include "insn_trans/trans_xthead.c.inc" -- 2.52.0
