From: Ruslan Ruslichenko <[email protected]> The patch implements TYPE_FDT_GENERIC_INTC interface, which enables GIC to be instantiated and wired via the device tree description.
The implemented interface method are following: 1. 'get_irq': Parses device tree interrupt specifiers and return correct qemu_irq for devices which has IRQ's wired to GIC. 2. 'auto_parent': Automatically connect the GIC's output signals to the CPU's found in current machine configuration. Signed-off-by: Ruslan Ruslichenko <[email protected]> --- hw/intc/arm_gic.c | 32 +++++++++++++++++++++++++ hw/intc/arm_gic_common.c | 50 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 4d4b79e6f3..2be44d8e5b 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -24,12 +24,15 @@ #include "gic_internal.h" #include "qapi/error.h" #include "hw/core/cpu.h" +#include "hw/core/boards.h" #include "qemu/log.h" #include "qemu/module.h" #include "trace.h" #include "system/kvm.h" #include "system/qtest.h" +#include "hw/core/fdt_generic_util.h" + /* #define DEBUG_GIC */ #ifdef DEBUG_GIC @@ -2162,12 +2165,41 @@ static void arm_gic_realize(DeviceState *dev, Error **errp) } +static void arm_gic_fdt_auto_parent(FDTGenericIntc *obj, Error **errp) +{ + GICState *s = ARM_GIC(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + int num_cpus = current_machine->smp.cpus; + CPUState *cs; + int i = 0; + + for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { + if (i >= s->num_cpu) { + break; + } + + sysbus_connect_irq(sbd, i, + qdev_get_gpio_in(DEVICE(cs), 0)); + sysbus_connect_irq(sbd, i + num_cpus, + qdev_get_gpio_in(DEVICE(cs), 1)); + sysbus_connect_irq(sbd, i + 2 * num_cpus, + qdev_get_gpio_in(DEVICE(cs), 2)); + sysbus_connect_irq(sbd, i + 3 * num_cpus, + qdev_get_gpio_in(DEVICE(cs), 3)); + i++; + } + + /* FIXME: Add some error checking */ +} + static void arm_gic_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc = DEVICE_CLASS(klass); ARMGICClass *agc = ARM_GIC_CLASS(klass); + FDTGenericIntcClass *fgic = FDT_GENERIC_INTC_CLASS(klass); device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize); + fgic->auto_parent = arm_gic_fdt_auto_parent; } static const TypeInfo arm_gic_info = { diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 304d89cf56..04787cff79 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -28,6 +28,8 @@ #include "migration/vmstate.h" #include "system/kvm.h" +#include "hw/core/fdt_generic_util.h" + static int gic_pre_save(void *opaque) { GICState *s = (GICState *)opaque; @@ -348,6 +350,51 @@ static void arm_gic_common_linux_init(ARMLinuxBootIf *obj, } } +static int arm_gic_common_fdt_get_irq(FDTGenericIntc *obj, qemu_irq *irqs, + uint32_t *cells, int ncells, int max, + Error **errp) +{ + GICState *gs = ARM_GIC_COMMON(obj); + int cpu = 0; + uint32_t idx; + + if (ncells != 3) { + error_setg(errp, "ARM GIC requires 3 interrupt cells, %d cells given", + ncells); + return 0; + } + idx = cells[1]; + + switch (cells[0]) { + case 0: + if (idx >= gs->num_irq) { + error_setg(errp, "ARM GIC SPI has maximum index of %" PRId32 ", " + "index %" PRId32 " given", gs->num_irq - 1, idx); + return 0; + } + (*irqs) = qdev_get_gpio_in(DEVICE(obj), cells[1]); + return 1; + case 1: /* PPI */ + if (idx >= 16) { + error_setg(errp, "ARM GIC PPI has maximum index of 15, " + "index %" PRId32 " given", idx); + return 0; + } + for (cpu = 0; cpu < max && cpu < gs->num_cpu; cpu++) { + if (cells[2] & 1 << (cpu + 8)) { + *irqs = qdev_get_gpio_in(DEVICE(obj), + gs->num_irq - 16 + idx + cpu * 32); + } + irqs++; + } + return cpu; + default: + error_setg(errp, "Invalid cell 0 value in interrupt binding: %d", + cells[0]); + return 0; + } +} + static const Property arm_gic_common_properties[] = { DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1), DEFINE_PROP_UINT32("first-cpu-index", GICState, first_cpu_index, 0), @@ -368,12 +415,14 @@ static void arm_gic_common_class_init(ObjectClass *klass, const void *data) DeviceClass *dc = DEVICE_CLASS(klass); ResettableClass *rc = RESETTABLE_CLASS(klass); ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass); + FDTGenericIntcClass *fgic = FDT_GENERIC_INTC_CLASS(klass); rc->phases.hold = arm_gic_common_reset_hold; dc->realize = arm_gic_common_realize; device_class_set_props(dc, arm_gic_common_properties); dc->vmsd = &vmstate_gic; albifc->arm_linux_init = arm_gic_common_linux_init; + fgic->get_irq = arm_gic_common_fdt_get_irq; } static const TypeInfo arm_gic_common_type = { @@ -385,6 +434,7 @@ static const TypeInfo arm_gic_common_type = { .abstract = true, .interfaces = (const InterfaceInfo[]) { { TYPE_ARM_LINUX_BOOT_IF }, + { TYPE_FDT_GENERIC_INTC }, { }, }, }; -- 2.43.0
