Hi Daniel, just a gentle poke. Thanks, Zhao
On Wed, Jan 07, 2026 at 11:42:27AM +0800, Zhao Liu wrote: > Date: Wed, 7 Jan 2026 11:42:27 +0800 > From: Zhao Liu <[email protected]> > Subject: Re: [PATCH 10/10] dosc/cpu-models-x86: Add documentation for > DiamondRapids > > Hi Daniel, > > > > +``DiamondRapids`` > > > + Intel Xeon Processor. > > > + > > > + Diamond Rapids product has a topology which differs from previous > > > Xeon > > > + products. It does not support SMT, but instead features a dual core > > > + module (DCM) architecture. It also has core building blocks (CBB - > > > die > > > + level in CPU topology). The cache hierarchy is organized as follows: > > > + L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per > > > + CBB. This cache topology can be emulated for DiamondRapids CPU model > > > + using the smp-cache configuration as shown below: > > > > Can I request a slight rewording to simplify this: > > Yes, of course. > > > ``DiamondRapids`` > > Intel Xeon Processor (DiamondRapids, 2025). This does not include SMT > > but allows the module and die topology levels. The cache hierarchy is > > L1 i/d cache per thread, L2 cache per module, and L3 cache per die, > > which can be emulated using using the smp-cache option: > > Thanks for your words! > > In the previous text, I also aimed to clarify the relationship between > DCM/CBB and the QEMU topology hierarchy, as these terms appear frequently > in DMR-related materials. Therefore, I thought a brief explanation of > DCM/CBB may be helpful: > > This does not include SMT but allows the module (dual core module - DCM) > and die (core building block - CBB) topology levels. > > What do you think? > > > > Example: > > > > :: > > > > -machine smp-cache.0.cache=l1d,smp-cache.0.topology=thread,\ > > smp-cache.1.cache=l1i,smp-cache.1.topology=thread,\ > > smp-cache.2.cache=l2,smp-cache.2.topology=module,\ > > smp-cache.3.cache=l3,smp-cache.3.topology=die,\ > > ... > > Thanks, > Zhao >
