[PATCH] riscv: correct fractional LMUL legality check in vsetvl

[Ridham Khurana]

---
 target/riscv/vector_helper.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 2de3358ee8..eff349841a 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -47,18 +47,12 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, 
target_ulong s1,
     target_ulong reserved = s2 &
                             MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
                                             xlen - 1 - R_VTYPE_RESERVED_SHIFT);
-    uint16_t vlen = cpu->cfg.vlenb << 3;
     int8_t lmul;
 
     if (vlmul & 4) {
-        /*
-         * Fractional LMUL, check:
-         *
-         * VLEN * LMUL >= SEW
-         * VLEN >> (8 - lmul) >= sew
-         * (vlenb << 3) >> (8 - lmul) >= sew
-         */
-        if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
+        /* fractional LMUL legality check: LMUL × ELEN ≥ SEW */
+        int divisor = 1 << (8 - vlmul); /* converts encoding into divisor for 
fractional LMUL */
+        if (vlmul == 4 || cpu->cfg.elen < sew * divisor) {
             vill = true;
         }
     }
-- 
2.49.0