On Thu, Nov 20, 2025 at 03:10:30PM +0800, Zhao Liu wrote:
> Current DiamondRapids hasn't supported cache model. Instead, document
> its special CPU & cache topology to allow user emulate with "-smp" &
> "-machine smp-cache".
>
> Cc: Yu Chen <[email protected]>
> Signed-off-by: Zhao Liu <[email protected]>
> ---
> docs/system/cpu-models-x86.rst.inc | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/docs/system/cpu-models-x86.rst.inc
> b/docs/system/cpu-models-x86.rst.inc
> index 6a770ca8351c..c4c8fc67a562 100644
> --- a/docs/system/cpu-models-x86.rst.inc
> +++ b/docs/system/cpu-models-x86.rst.inc
> @@ -71,6 +71,26 @@ mixture of host CPU models between machines, if live
> migration
> compatibility is required, use the newest CPU model that is compatible
> across all desired hosts.
>
> +``DiamondRapids``
> + Intel Xeon Processor.
> +
> + Diamond Rapids product has a topology which differs from previous Xeon
> + products. It does not support SMT, but instead features a dual core
> + module (DCM) architecture. It also has core building blocks (CBB - die
> + level in CPU topology). The cache hierarchy is organized as follows:
> + L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per
> + CBB. This cache topology can be emulated for DiamondRapids CPU model
> + using the smp-cache configuration as shown below:
Can I request a slight rewording to simplify this:
``DiamondRapids``
Intel Xeon Processor (DiamondRapids, 2025). This does not include SMT
but allows the module and die topology levels. The cache hierarchy is
L1 i/d cache per thread, L2 cache per module, and L3 cache per die,
which can be emulated using using the smp-cache option:
Example:
::
-machine smp-cache.0.cache=l1d,smp-cache.0.topology=thread,\
smp-cache.1.cache=l1i,smp-cache.1.topology=thread,\
smp-cache.2.cache=l2,smp-cache.2.topology=module,\
smp-cache.3.cache=l3,smp-cache.3.topology=die,\
...
With regards,
Daniel
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