From: Nicolin Chen <[email protected]> Introduce a reset handler for the Tegra241 CMDQV and initialize its register state.
CMDQV gets initialized early during guest boot, hence the handler verifies that at least one cold-plugged device is attached to the associated vIOMMU before proceeding. This is required to retrieve host CMDQV info and to validate it against the QEMU implementation support. Signed-off-by: Nicolin Chen <[email protected]> Signed-off-by: Shameer Kolothum <[email protected]> --- hw/arm/smmuv3.c | 1 + hw/arm/tegra241-cmdqv.c | 105 ++++++++++++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.h | 7 +++ hw/arm/trace-events | 1 + 4 files changed, 114 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 02e1a925a4..ec8687d39a 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1943,6 +1943,7 @@ static void smmu_reset_exit(Object *obj, ResetType type) smmuv3_reset(s); smmuv3_accel_reset(s); + tegra241_cmdqv_reset(s); } static bool smmu_validate_property(SMMUv3State *s, Error **errp) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 5b8a7bdff2..1f62b7627a 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -592,6 +592,111 @@ bool tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, return true; } +static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv) +{ + SMMUv3AccelState *s_accel = s->s_accel; + uint32_t data_type = IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV; + struct iommu_hw_info_tegra241_cmdqv cmdqv_info; + SMMUv3AccelDevice *accel_dev; + Error *local_err = NULL; + uint64_t caps; + int i; + + if (QLIST_EMPTY(&s_accel->device_list)) { + error_report("tegra241-cmdqv=on: requires at least one cold-plugged " + "vfio-pci device"); + goto out_err; + } + + accel_dev = QLIST_FIRST(&s_accel->device_list); + if (!iommufd_backend_get_device_info(accel_dev->idev->iommufd, + accel_dev->idev->devid, + &data_type, &cmdqv_info, + sizeof(cmdqv_info), &caps, + NULL, &local_err)) { + error_append_hint(&local_err, "Failed to get Host CMDQV device info"); + error_report_err(local_err); + goto out_err; + } + + if (data_type != IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV) { + error_report("Wrong data type (%d) from Host CMDQV device info", + data_type); + goto out_err; + } + if (cmdqv_info.version != TEGRA241_CMDQV_VERSION) { + error_report("Wrong version (%d) from Host CMDQV device info", + cmdqv_info.version); + goto out_err; + } + if (cmdqv_info.log2vcmdqs != TEGRA241_CMDQV_NUM_CMDQ_LOG2) { + error_report("Wrong num of cmdqs (%d) from Host CMDQV device info", + cmdqv_info.version); + goto out_err; + } + if (cmdqv_info.log2vsids != TEGRA241_CMDQV_NUM_SID_PER_VM_LOG2) { + error_report("Wrong num of SID per VM (%d) from Host CMDQV device info", + cmdqv_info.version); + goto out_err; + } + + cmdqv->config = V_CONFIG_RESET; + cmdqv->param = + FIELD_DP32(cmdqv->param, PARAM, CMDQV_VER, TEGRA241_CMDQV_VERSION); + cmdqv->param = FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_CMDQ_LOG2, + TEGRA241_CMDQV_NUM_CMDQ_LOG2); + cmdqv->param = FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_SID_PER_VM_LOG2, + TEGRA241_CMDQV_NUM_SID_PER_VM_LOG2); + trace_tegra241_cmdqv_init_regs(cmdqv->param); + cmdqv->status = R_STATUS_CMDQV_ENABLED_MASK; + for (i = 0; i < 2; i++) { + cmdqv->vi_err_map[i] = 0; + cmdqv->vi_int_mask[i] = 0; + cmdqv->cmdq_err_map[i] = 0; + } + cmdqv->vintf_config = 0; + cmdqv->vintf_status = 0; + for (i = 0; i < 4; i++) { + cmdqv->vintf_cmdq_err_map[i] = 0; + } + for (i = 0; i < 128; i++) { + cmdqv->cmdq_alloc_map[i] = 0; + cmdqv->vcmdq_cons_indx[i] = 0; + cmdqv->vcmdq_prod_indx[i] = 0; + cmdqv->vcmdq_config[i] = 0; + cmdqv->vcmdq_status[i] = 0; + cmdqv->vcmdq_gerror[i] = 0; + cmdqv->vcmdq_gerrorn[i] = 0; + cmdqv->vcmdq_base[i] = 0; + cmdqv->vcmdq_cons_indx_base[i] = 0; + } + return; + +out_err: + exit(1); +} + +void tegra241_cmdqv_reset(SMMUv3State *s) +{ + SMMUv3AccelState *s_accel = s->s_accel; + Tegra241CMDQV *cmdqv = s->cmdqv; + int i; + + if (!s_accel || !cmdqv) { + return; + } + + for (i = 127; i >= 0; i--) { + if (cmdqv->vcmdq[i]) { + iommufd_backend_free_id(s_accel->viommu.iommufd, + cmdqv->vcmdq[i]->hw_queue_id); + g_free(cmdqv->vcmdq[i]); + cmdqv->vcmdq[i] = NULL; + } + } + tegra241_cmdqv_init_regs(s, cmdqv); +} + void tegra241_cmdqv_init(SMMUv3State *s) { SysBusDevice *sbd = SYS_BUS_DEVICE(OBJECT(s)); diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 97eaef8a72..0e8729c0b0 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -13,6 +13,9 @@ #include "hw/registerfields.h" #include CONFIG_DEVICES +#define TEGRA241_CMDQV_VERSION 0x1 +#define TEGRA241_CMDQV_NUM_CMDQ_LOG2 0x1 +#define TEGRA241_CMDQV_NUM_SID_PER_VM_LOG2 0x4 #define TEGRA241_CMDQV_IO_LEN 0x50000 typedef struct Tegra241CMDQV { @@ -314,11 +317,15 @@ A_VINTFi_CONFIG(0) #ifdef CONFIG_TEGRA241_CMDQV bool tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, uint32_t *out_viommu_id, Error **errp); +void tegra241_cmdqv_reset(SMMUv3State *s); void tegra241_cmdqv_init(SMMUv3State *s); #else static inline void tegra241_cmdqv_init(SMMUv3State *s) { } +static inline void tegra241_cmdqv_reset(SMMUv3State *s) +{ +} static inline bool tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, uint32_t *out_viommu_id, Error **errp) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 76bda0efef..ef495c040c 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -74,6 +74,7 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type, uint32_t hwpt_id) "vS # tegra241-cmdqv tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32_t map0) "hw irq received. error (hex) maps: %04X:%04X:%04X:%04X" +tegra241_cmdqv_init_regs(uint32_t param) "hw info received. param: 0x%04X" # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity, int data_bits, int stop_bits) "%s speed=%d parity=%c data=%d stop=%d" -- 2.43.0
