On Mon, Dec 01, 2025 at 06:01:48PM +0100, Paolo Bonzini wrote: > Date: Mon, 1 Dec 2025 18:01:48 +0100 > From: Paolo Bonzini <[email protected]> > Subject: Re: [PATCH v4 17/23] i386/cpu: Migrate MSR_IA32_PL0_SSP for FRED > and CET-SHSTK > > On 11/18/25 04:42, Zhao Liu wrote: > > From: "Xin Li (Intel)" <[email protected]> > > > > Both FRED and CET-SHSTK need MSR_IA32_PL0_SSP, so add the vmstate for > > this MSR. > > > > When CET-SHSTK is not supported, MSR_IA32_PL0_SSP keeps accessible, but > > its value doesn't take effect. Therefore, treat this vmstate as a > > subsection rather than a fix for the previous FRED vmstate. > > > > Tested-by: Farrah Chen <[email protected]> > > Signed-off-by: Xin Li (Intel) <[email protected]> > > Co-developed-by: Zhao Liu <[email protected]> > > Signed-off-by: Zhao Liu <[email protected]> > > --- > > Changes Since v3: > > - New commit. > > --- > > target/i386/machine.c | 26 ++++++++++++++++++++++++++ > > 1 file changed, 26 insertions(+) > > > > diff --git a/target/i386/machine.c b/target/i386/machine.c > > index 45b7cea80aa7..0a756573b6cd 100644 > > --- a/target/i386/machine.c > > +++ b/target/i386/machine.c > > @@ -1668,6 +1668,31 @@ static const VMStateDescription vmstate_triple_fault > > = { > > } > > }; > > +static bool pl0_ssp_needed(void *opaque) > > +{ > > + X86CPU *cpu = opaque; > > + CPUX86State *env = &cpu->env; > > + > > +#ifdef TARGET_X86_64 > > + if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) { > > + return true; > > + } > > +#endif > > + > > + return !!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK); > > Can you just make it return "!!(env->pl0_ssp)"? If all of these bits are > zero the MSR will not be settable, and this way you can migrate VMs as long > as they don't use PL0_SSP.
Yes, it's a good idea. Thanks, Zhao
