Hi Cédric, >-----Original Message----- >From: Cédric Le Goater <[email protected]> >Subject: Re: [PATCH v8 17/23] vfio/listener: Bypass readonly region for dirty >tracking > >Hello Zhenzhong, > >On 11/28/25 03:08, Duan, Zhenzhong wrote: >> Hi Yi, Cedric, >> >> Could you also help comment on this patch? This is a pure VFIO migration >related optimization, I think it's better to let it go with the "vfio: relax >the >vIOMMU check" series. >> I'd like to move it in next respin of "vfio: relax the vIOMMU check" series >> if >you think it make sense. > >IMO, the "vfio: relax the vIOMMU check" is fine as it is. > >I would instead introduce a new series to handle ERRATA_772415 >since it is a special case of "intel_iommu: Enable first stage >translation for passthrough device". > >So we would have 3 series (in order of appearance on the list) : > >1. "vfio: relax the vIOMMU check" >2. "intel_iommu: Enable first stage translation for passthrough > device" without quirks >3. "vfio: handle ERRATA_772415" with the quirk part, so that's > patch 17,19,20,21 ? > > >Series 2 seems the most important, as it sets the foundation >for the other architectures which have a need for nested >IOMMU support (smmu/nvidia). Series 1 is nice to have. >Series 3. is an extension of 2. for broken HW.
Good suggestion to split out ERRATA_772415 from the base nesting series. There is some code in patch17 which is needed by ERRATA_772415, it makes sense to move it to ERRATA_772415 series. > >For the next iterations (QEMU 11.0), let's get series 2. in >first. I have been including it in my QEMU tree for a while >now I didn't see any regression. Should be fine. > >Then, we can merge 1. and 3. through the vfio queue. Shouldn't >be a major task now that we had all these reviews. > >How's that ? Good for me. Then I'll send series2, then series1, finally series3 in order. I'd like to wait a few days to collect comments before sending v9 of series2 because the split of series2 and series 3 involves only patch reorder and no code changes. > > >btw, > > Reference from 4th Gen Intel Xeon Processor Scalable Family >Specification > Update, Errata Details, SPR17. > >https://edc.intel.com/content/www/us/en/design/products-and-solutions/pr >ocessors-and-chipsets/eagle-stream/sapphire-rapids-specification-update/ > >Url is not accessible (for me). Me too, will update. https://cdrdv2.intel.com/v1/dl/getContent/772415 is accessible for me now. BRs, Zhenzhong
