RISC-V vector "elements are simply packed in order from the least-signicant to most-signicant bits of the vector register" [*] which is little endianness, therefore the cpu_ld/st_data*() definitions expand to the little endian declarations. Use the explicit little-endian variants.
[*] RISC-V "V" Vector Extension v1.0 Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> --- target/riscv/vector_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 2de3358ee86..caa8dd9c125 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -193,9 +193,9 @@ void NAME##_host(void *vd, uint32_t idx, void *host) \ } GEN_VEXT_LD_ELEM(lde_b, uint8_t, H1, ldub) -GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw) -GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl) -GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq) +GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw_le) +GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl_le) +GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq_le) #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ static inline QEMU_ALWAYS_INLINE \ @@ -214,9 +214,9 @@ void NAME##_host(void *vd, uint32_t idx, void *host) \ } GEN_VEXT_ST_ELEM(ste_b, uint8_t, H1, stb) -GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw) -GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl) -GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq) +GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw_le) +GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl_le) +GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq_le) static inline QEMU_ALWAYS_INLINE void vext_continuous_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_tlb, -- 2.51.0
