Signed-off-by: Eric Huang <[email protected]>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 72 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 73 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 75f4e434085..44ac0a3d29e 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -56,6 +56,7 @@
#define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon")
#define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nanhu")
#define TYPE_RISCV_CPU_XIANGSHAN_KMH
RISCV_CPU_TYPE_NAME("xiangshan-kunminghu")
+#define TYPE_RISCV_CPU_LEAPFIVE_V1 RISCV_CPU_TYPE_NAME("leapfive-v1")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 73d4280d7c8..30cda2212c6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3306,6 +3306,78 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.max_satp_mode = VM_1_10_SV48,
),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_LEAPFIVE_V1, TYPE_RISCV_VENDOR_CPU,
+ .misa_mxl_max = MXL_RV64,
+ .misa_ext = RVG | RVC | RVS | RVU | RVH | RVV,
+ .priv_spec = PRIV_VERSION_1_13_0,
+
+ /* victory-v1 V extenson/configs */
+ .cfg.vlenb = 64,
+ .cfg.elen = 64,
+
+ /* Unprivileged ISA Extensions */
+ .cfg.ext_zawrs = true,
+ .cfg.ext_zama16b = true,
+ .cfg.ext_zba = true,
+ .cfg.ext_zbb = true,
+ .cfg.ext_zbc = true,
+ .cfg.ext_zbs = true,
+ .cfg.ext_zcb = true,
+ .cfg.ext_zcmop = true,
+ .cfg.ext_zimop = true,
+ .cfg.ext_ziccrse = true,
+ .cfg.ext_zfa = true,
+ .cfg.ext_zfhmin = true,
+ .cfg.ext_zfbfmin = true,
+
+ .cfg.ext_zic64b = true,
+ .cfg.ext_zicntr = true,
+ .cfg.ext_zicond = true,
+ .cfg.ext_zicsr = true,
+ .cfg.ext_zifencei = true,
+ .cfg.ext_zihintntl = true,
+ .cfg.ext_zihintpause = true,
+ .cfg.ext_zihpm = true,
+
+ .cfg.ext_zkt = true,
+ .cfg.ext_zvbb = true,
+ .cfg.ext_zvbc = true,
+ .cfg.ext_zvfhmin = true,
+ .cfg.ext_zvfbfwma = true,
+ .cfg.ext_zvfbfmin = true,
+ .cfg.ext_zvkt = true,
+ .cfg.ext_zvkn = true,
+ .cfg.ext_zvkg = true,
+ .cfg.ext_sha = true,
+
+ /* Privileged ISA Extensions */
+ .cfg.ext_smaia = true,
+ .cfg.ext_smepmp = true,
+ .cfg.ext_smstateen = true,
+ .cfg.ext_ssaia = true,
+ .cfg.ext_sscofpmf = true,
+ .cfg.ext_sstc = true,
+ .cfg.ext_svinval = true,
+ .cfg.ext_svnapot = true,
+ .cfg.ext_smnpm = true,
+ .cfg.ext_svpbmt = true,
+ .cfg.ext_ssnpm = true,
+ .cfg.ext_svvptc = true,
+ .cfg.ext_sspm = true,
+ .cfg.ext_supm = true,
+ .cfg.ext_svade = true,
+
+ .cfg.ext_zicbom = true,
+ .cfg.ext_zicbop = true,
+ .cfg.ext_zicboz = true,
+ .cfg.cbom_blocksize = 64,
+ .cfg.cbop_blocksize = 64,
+ .cfg.cboz_blocksize = 64,
+ .cfg.mmu = true,
+ .cfg.pmp = true,
+ .cfg.max_satp_mode = VM_1_10_SV48,
+ ),
+
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
.cfg.max_satp_mode = VM_1_10_SV57,
--
2.34.1
