On Thu, Nov 20, 2025 at 11:06 PM Philippe Mathieu-Daudé <[email protected]> wrote: > > On 21/11/25 06:01, Jamin Lin via wrote:
Thank you for the quick turnaround on the bug fix, Jamin! Tested it against internal models on our end. Hotplugged devices now appear with `lspci`. > > This patch updates the ASPEED PCIe Root Port capability layout and interrupt > > handling to match the hardware-defined capability structure as documented in > > the PCI Express Controller (PCIE) chapter of the ASPEED SoC datasheet. > > > > The following capability offsets and fields are now aligned with the actual > > hardware implementation (validated using EVB config-space dumps via > > 'lspci -s <bdf> -vvv'): > > > > - Added MSI capability at offset 0x50 and enabled 1-vector MSI support > > - Added PCI Express Capability structure at offset 0x80 > > - Added Secondary Subsystem Vendor ID (SSVID) at offset 0xC0 > > - Added AER capability at offset 0x100 > > - Implemented aer_vector() callback and MSI init/uninit hooks > > - Updated Root Port SSID to 0x1150 to reflect the platform default > > > > Enabling MSI is required for proper PCIe Hotplug event signaling. This > > change > > improves correctness and ensures QEMU Root Port behavior matches the > > behavior > > of ASPEED hardware and downstream kernel expectations. > > > > Signed-off-by: Jamin Lin <[email protected]> > > --- > > hw/pci-host/aspeed_pcie.c | 40 ++++++++++++++++++++++++++++++++++++++- > > 1 file changed, 39 insertions(+), 1 deletion(-) > > Reviewed-by: Philippe Mathieu-Daudé <[email protected]> > Reviewed-by: Nabih Estefan <[email protected]> Tested-by: Nabih Estefan <[email protected]>
