Add a CPU entry for the RV64 SiFive U74 CPU .It is available in single-core and dual-core configurations,and features advanced power management and AIA compliance.More details can be found at https://www.sifive.com/document-file/sifive-essential-u7-product-brief
Signed-off-by: TravisYang <[email protected]> --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 44 ++++++++++++++++++++++++++++++++++++------ 2 files changed, 39 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 1fc8140190..f17390d072 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -57,6 +57,7 @@ #define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nanhu") #define TYPE_RISCV_CPU_XIANGSHAN_KMH RISCV_CPU_TYPE_NAME("xiangshan-kunminghu") #define TYPE_RISCV_CPU_THEAD_C910 RISCV_CPU_TYPE_NAME("thead-c910") +#define TYPE_RISCV_CPU_SIFIVE_U74 RISCV_CPU_TYPE_NAME("sifive-u74") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ea9e6eb6a5..aa2fc59804 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3284,10 +3284,10 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.pmp = true, .cfg.max_satp_mode = VM_1_10_SV48, ), - + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C910, TYPE_RISCV_VENDOR_CPU, .misa_mxl_max = MXL_RV64, - .misa_ext = RVG | RVC | RVS | RVU, + .misa_ext = RVG | RVC | RVS | RVU, .priv_spec = PRIV_VERSION_1_12_0, .cfg.ext_zcf = true, @@ -3297,9 +3297,9 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.ext_zfhmin = true, .cfg.mmu = true, - .cfg.ext_xtheadba = true, - .cfg.ext_xtheadbb = true, - .cfg.ext_xtheadbs = true, + .cfg.ext_xtheadba = true, + .cfg.ext_xtheadbb = true, + .cfg.ext_xtheadbs = true, .cfg.ext_xtheadcmo = true, .cfg.ext_xtheadcondmov = true, .cfg.ext_xtheadfmemidx = true, @@ -3328,9 +3328,41 @@ static const TypeInfo riscv_cpu_type_infos[] = { .cfg.max_satp_mode = VM_1_10_SV39, #ifndef CONFIG_USER_ONLY .custom_csrs = th_csr_list, -#endif +#endif ), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U74, TYPE_RISCV_CPU_SIFIVE_U, + .misa_mxl_max = MXL_RV64, + .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVH, + .priv_spec = PRIV_VERSION_1_12_0, + + .cfg.mmu = true, + .cfg.pmp_regions = 16, + + .cfg.ext_zba = true, + .cfg.ext_zbb = true, + .cfg.ext_zbs = true, + .cfg.ext_zic64b = true, + + .cfg.ext_zicbom = true, + .cfg.ext_zicboz = true, + .cfg.ext_zicbop = true, + + .cfg.ext_svinval = true, + .cfg.ext_svadu = true, + + .cfg.ext_zfh = true, + .cfg.ext_zfhmin = true, + .cfg.ext_zfa = true, + + .cfg.ext_smaia = true, + .cfg.ext_ssaia = true, + + .cfg.ext_sscofpmf = true, + .cfg.ext_sstc = true, + + .cfg.max_satp_mode = VM_1_10_SV39, + ), #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, -- 2.34.1
