On 29/09/25, Philippe Mathieu-Daudé wrote: > Hi, > > > On 29/9/25 13:55, Valentin Haudiquet wrote: > > From: vhaudiquet <[email protected]> > > > > Three instructions were not using the endianness swap flag, which resulted > > in a bug on big-endian architectures. > > I suppose you mean "big-endian host architectures". > If so, please clarify. > > > > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3131 > > Buglink: https://bugs.launchpad.net/ubuntu/+source/qemu/+bug/2123828 > > > > Signed-off-by: Valentin Haudiquet <[email protected]> > > --- > > target/riscv/insn_trans/trans_rvzce.c.inc | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc > > b/target/riscv/insn_trans/trans_rvzce.c.inc > > index c77c2b927b..dd15af0f54 100644 > > --- a/target/riscv/insn_trans/trans_rvzce.c.inc > > +++ b/target/riscv/insn_trans/trans_rvzce.c.inc > > @@ -88,13 +88,13 @@ static bool trans_c_lbu(DisasContext *ctx, arg_c_lbu *a) > > static bool trans_c_lhu(DisasContext *ctx, arg_c_lhu *a) > > { > > REQUIRE_ZCB(ctx); > > - return gen_load(ctx, a, MO_UW); > > + return gen_load(ctx, a, MO_TEUW); > NAck. > Please do not use MO_TE* anymore. Use explicit endianness. > > So far all our RISC-V targets are little-endian: > > $ git grep TARGET_BIG_ENDIAN configs/targets/riscv* > $ > > If you are not worried about RISCV core running in BE mode > (as we currently don't check MSTATUS_[USM]BE bits), your change > should be: > > - return gen_load(ctx, a, MO_UW); > + return gen_load(ctx, a, MO_UW | MO_LE); > > > } > > Regards, > > Phil.
Right, I forgot about the MO_TE changes when reviewing. My bad. //Anton
