Hi, This series implements the Efficient Trace (e-trace) for RISC-V [1]. This is a hardware level trace similar to what we found in other archs like ARM's CoreSight. The implementation is based on [1] and also on the RISC-V Trace Control Interface Specification [2].
Only a subset of all available features are implemented in this work. The idea is to contribute it back and allow others to keep incrementing it on demand. The design implemented is the simplest topology allowed by the specs: one trace encoder/trace ram sink pair per CPU. This topology was added in the 'virt' machine. We took kernel side considerations when adding the FDT for these components. More info on patch 05. A lot of design decisions/simplifications were made considering how the TCG emulation works. I attempted to justify them in the commit messages when relevant. Linux kernel driver support is available here: https://lore.kernel.org/linux-riscv/[email protected]/ It includes steps on how to test both the kernel and QEMU support in its cover letter. I'll add those steps in our own QEMU documentation, including the capabilities implemented, limitations and so on, in the following versions of this work. @Richard: if you could take a look at patch 07 I appreciate it. We've run out of tb_flags in RISC-V DisasContext and I had to be "creative" to avoid calling trace helpers without a trace session opened. Patches based on alistair/riscv-to-apply.next. You can also find them here: https://gitlab.com/danielhb/qemu/-/tree/rv-etrace Daniel Henrique Barboza (16): hw/riscv: Trace Encoder initial impl hw/riscv: Trace RAM Sink initial impl hw/riscv/trace-encoder: add trace start/stop logic hw/riscv/virt.c: add trace encoders and trace ram sinks hw/riscv: add e-trace message helpers target/riscv: add initial trace instrumentation hw/riscv/trace-encoder: write e-trace packets to RAM sink test/qtest: add riscv-trace-test.c hw/riscv/rv-trace-messages.c: add encoded trap message hw/riscv, target/riscv: send trace trap messages target/riscv, hw/riscv: send trace ppccd packets hw/riscv/trace: add format2 msg helper hw/riscv, target/riscv: send resync updiscon trace packets hw/riscv/rv-trace-messages: add format 1 msgs with branch info hw/riscv/trace-encoder: send branches info hw/riscv/trace: update branch bit in sync messages Mayuresh Chitale (1): hw/riscv/virt.c add trace encoder and ramsink fdt nodes hw/riscv/Kconfig | 5 + hw/riscv/meson.build | 2 + hw/riscv/rv-trace-messages.c | 373 +++++++++++ hw/riscv/rv-trace-messages.h | 40 ++ hw/riscv/trace-encoder.c | 609 ++++++++++++++++++ hw/riscv/trace-encoder.h | 62 ++ hw/riscv/trace-events | 9 + hw/riscv/trace-ram-sink.c | 263 ++++++++ hw/riscv/trace-ram-sink.h | 83 +++ hw/riscv/virt.c | 135 ++++ include/hw/riscv/virt.h | 2 + target/riscv/cpu.h | 11 + target/riscv/cpu_helper.c | 26 +- target/riscv/helper.h | 6 + .../riscv/insn_trans/trans_privileged.c.inc | 11 + target/riscv/insn_trans/trans_rvi.c.inc | 15 + target/riscv/meson.build | 3 +- target/riscv/tcg/tcg-cpu.c | 5 + target/riscv/trace_helper.c | 62 ++ target/riscv/translate.c | 21 + tests/qtest/meson.build | 2 +- tests/qtest/riscv-trace-test.c | 120 ++++ 22 files changed, 1862 insertions(+), 3 deletions(-) create mode 100644 hw/riscv/rv-trace-messages.c create mode 100644 hw/riscv/rv-trace-messages.h create mode 100644 hw/riscv/trace-encoder.c create mode 100644 hw/riscv/trace-encoder.h create mode 100644 hw/riscv/trace-ram-sink.c create mode 100644 hw/riscv/trace-ram-sink.h create mode 100644 target/riscv/trace_helper.c create mode 100644 tests/qtest/riscv-trace-test.c -- 2.51.0
