On Sat, Aug 16, 2025 at 12:08 AM Vladimir Isaev <[email protected]> wrote: > > opcode_at is used only in semihosting checks to match opcodes with expected > pattern. > > This is not a translator and if we got following assert if page is not in TLB: > qemu-system-riscv64: ../accel/tcg/translator.c:363: record_save: Assertion > `offset == db->record_start + db->record_len' failed. > > Fixes: 1f9c4462334f ("target/riscv: Use translator_ld* for everything") > Signed-off-by: Vladimir Isaev <[email protected]>
Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/translate.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index b1e41cdbf1f6..980a67ea855e 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -25,6 +25,7 @@ > #include "exec/helper-gen.h" > > #include "exec/translator.h" > +#include "exec/cpu_ldst.h" > #include "exec/log.h" > #include "semihosting/semihost.h" > > @@ -1143,7 +1144,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, > target_ulong pc) > CPUState *cpu = ctx->cs; > CPURISCVState *env = cpu_env(cpu); > > - return translator_ldl(env, &ctx->base, pc); > + return cpu_ldl_code(env, pc); > } > > #define SS_MMU_INDEX(ctx) (ctx->mem_idx | MMU_IDX_SS_WRITE) > -- > 2.50.1 > >
