Hi Zhenzhnog Reviewed-by: Clément Mathieu--Drif <[email protected]>
Thanks On Fri, 2025-09-19 at 03:06 -0400, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > According to VTD spec rev 4.1 section 6.6: > "For implementations reporting the Enhanced Set Root Table Pointer Support > (ESRTPS) field as Clear, on a 'Set Root Table Pointer' operation, software > must perform a global invalidate of the context cache, PASID-cache (if > applicable), and IOTLB, in that order. This is required to ensure hardware > references only the remapping structures referenced by the new root table > pointer and not stale cached entries. > > For implementations reporting the Enhanced Set Root Table Pointer Support > (ESRTPS) field as Set, as part of 'Set Root Table Pointer' operation, > hardware performs global invalidation on all DMA remapping translation > caches and hence software is not required to perform additional > invalidations" > > We already implemented ESRTPS capability in vtd_handle_gcmd_srtp() by > calling vtd_reset_caches(), just set ESRTPS in DMAR_CAP_REG to avoid > unnecessary global invalidation requests of context, PASID-cache and > IOTLB from guest. > > This change doesn't impact migration as the content of DMAR_CAP_REG is > migrated too. > > Signed-off-by: Zhenzhong Duan > <[[email protected]](mailto:[email protected])> > --- > hw/i386/intel_iommu_internal.h | 1 + > hw/i386/intel_iommu.c | 2 +- > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h > index 360e937989..5dd92d388d 100644 > --- a/hw/i386/intel_iommu_internal.h > +++ b/hw/i386/intel_iommu_internal.h > @@ -214,6 +214,7 @@ > #define VTD_CAP_DRAIN_WRITE (1ULL << 54) > #define VTD_CAP_DRAIN_READ (1ULL << 55) > #define VTD_CAP_FS1GP (1ULL << 56) > +#define VTD_CAP_ESRTPS (1ULL << 63) > #define VTD_CAP_DRAIN (VTD_CAP_DRAIN_READ | > VTD_CAP_DRAIN_WRITE) > #define VTD_CAP_CM (1ULL << 7) > #define VTD_PASID_ID_SHIFT 20 > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index 83c5e44413..f04300022e 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -4549,7 +4549,7 @@ static void vtd_cap_init(IntelIOMMUState *s) > > s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | > VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS | > - VTD_CAP_MGAW(s->aw_bits); > + VTD_CAP_ESRTPS | VTD_CAP_MGAW(s->aw_bits); > if (s->dma_drain) { > s->cap |= VTD_CAP_DRAIN; > } > -- > 2.47.1 >
