From: Kane-Chen-AS <[email protected]> AST27x0 platforms support two LTPI controllers. Each LTPI controller has one set of device registers, one set of PHY register and one OEM channel for AST1700 connection.
Signed-off-by: Kane-Chen-AS <[email protected]> --- include/hw/arm/aspeed_soc.h | 4 ++ include/hw/misc/aspeed_ltpi.h | 25 ++++++++ hw/arm/aspeed_ast27x0.c | 28 +++++++++ hw/misc/aspeed_ltpi.c | 111 ++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + 5 files changed, 169 insertions(+) create mode 100644 include/hw/misc/aspeed_ltpi.h create mode 100644 hw/misc/aspeed_ltpi.c diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 77263cc6ec..72eefb0327 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -41,6 +41,7 @@ #include "hw/fsi/aspeed_apb2opb.h" #include "hw/char/serial-mm.h" #include "hw/intc/arm_gicv3.h" +#include "hw/misc/aspeed_ltpi.h" #define ASPEED_SPIS_NUM 3 #define ASPEED_EHCIS_NUM 4 @@ -104,6 +105,7 @@ struct AspeedSoCState { UnimplementedDeviceState ltpi; UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; AspeedAPB2OPBState fsi[2]; + AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM]; uint8_t ioexp_num; }; @@ -287,6 +289,8 @@ enum { ASPEED_GIC_REDIST, ASPEED_DEV_IPC0, ASPEED_DEV_IPC1, + ASPEED_DEV_LTPI_CTRL1, + ASPEED_DEV_LTPI_CTRL2, }; qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); diff --git a/include/hw/misc/aspeed_ltpi.h b/include/hw/misc/aspeed_ltpi.h new file mode 100644 index 0000000000..2c31a555dd --- /dev/null +++ b/include/hw/misc/aspeed_ltpi.h @@ -0,0 +1,25 @@ +/* + * ASPEED LTPI Controller + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ASPEED_LTPI_H +#define ASPEED_LTPI_H + +#include "hw/sysbus.h" + +#define TYPE_ASPEED_LTPI "aspeed.ltpi-ctrl" +OBJECT_DECLARE_SIMPLE_TYPE(AspeedLTPIState, ASPEED_LTPI) + +#define ASPEED_LTPI_NR_REGS (0x900 >> 2) + +struct AspeedLTPIState { + SysBusDevice parent; + MemoryRegion mmio; + + uint32_t regs[ASPEED_LTPI_NR_REGS]; +}; + +#endif /* ASPEED_LTPI_H */ diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 6aa3841b69..3f93554027 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -80,6 +80,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = { [ASPEED_DEV_UART10] = 0x14C33900, [ASPEED_DEV_UART11] = 0x14C33A00, [ASPEED_DEV_UART12] = 0x14C33B00, + [ASPEED_DEV_LTPI_CTRL1] = 0x14C34000, + [ASPEED_DEV_LTPI_CTRL2] = 0x14C35000, [ASPEED_DEV_WDT] = 0x14C37000, [ASPEED_DEV_SPI_BOOT] = 0x100000000, [ASPEED_DEV_LTPI] = 0x300000000, @@ -531,6 +533,12 @@ static void aspeed_soc_ast2700_init(Object *obj) TYPE_UNIMPLEMENTED_DEVICE); } +static void aspeed_ast2700_ast1700_init(AspeedSoCState *s, int i) +{ + object_initialize_child(OBJECT(s), "ltpi-ctrl[*]", + &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI); +} + /* * ASPEED ast2700 has 0x0 as cluster ID * @@ -610,6 +618,20 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp) return true; } +static void aspeed_soc_ast2700_ast1700_realize(Aspeed27x0SoCState *a, + AspeedSoCState *s, + AspeedSoCClass *sc, + int index, Error **errp) +{ + AspeedLTPIState *ltpi_ctrl = ASPEED_LTPI(&s->ltpi_ctrl[index]); + hwaddr ltpi_base = sc->memmap[ASPEED_DEV_LTPI_CTRL1 + index]; + + if (!sysbus_realize(SYS_BUS_DEVICE(ltpi_ctrl), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base); +} + static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) { int i; @@ -936,6 +958,12 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); + /* I/O Expander */ + for (i = 0; i < s->ioexp_num; i++) { + aspeed_ast2700_ast1700_init(s, i); + aspeed_soc_ast2700_ast1700_realize(a, s, sc, i, errp); + } + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], diff --git a/hw/misc/aspeed_ltpi.c b/hw/misc/aspeed_ltpi.c new file mode 100644 index 0000000000..0c9cf40094 --- /dev/null +++ b/hw/misc/aspeed_ltpi.c @@ -0,0 +1,111 @@ +/* + * ASPEED LTPI Controller + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/misc/aspeed_ltpi.h" + +#define LTPI_LINK_MNG 0x42 +#define LTPI_PHY_MODE 0x80 + +static uint64_t ltpi_read(void *opaque, hwaddr offset, unsigned size) +{ + AspeedLTPIState *s = opaque; + uint32_t idx = offset >> 2; + + if (idx >= ASPEED_LTPI_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad offset=0x%" HWADDR_PRIx "\n", + TYPE_ASPEED_LTPI, offset); + return 0; + } + + return s->regs[idx]; +} + +static void ltpi_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) +{ + AspeedLTPIState *s = opaque; + uint32_t idx = offset >> 2; + + if (idx >= ASPEED_LTPI_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad offset=0x%" HWADDR_PRIx " val=0x%" PRIx64 "\n", + TYPE_ASPEED_LTPI, offset, val); + return; + } + + switch (offset) { + default: + s->regs[idx] = (uint32_t)val; + break; + } +} + +static const MemoryRegionOps ltpi_ops = { + .read = ltpi_read, + .write = ltpi_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + }, +}; + +static void ltpi_reset(DeviceState *dev) +{ + AspeedLTPIState *s = ASPEED_LTPI(dev); + memset(s->regs, 0, sizeof(s->regs)); + /* set default values */ + s->regs[LTPI_LINK_MNG] = 0x11900007; + s->regs[LTPI_PHY_MODE] = 0x2; +} + + +static const VMStateDescription vmstate_ltpi = { + .name = TYPE_ASPEED_LTPI, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AspeedLTPIState, + ASPEED_LTPI_NR_REGS), + VMSTATE_END_OF_LIST() + } +}; + +static void ltpi_realize(DeviceState *dev, Error **errp) +{ + AspeedLTPIState *s = ASPEED_LTPI(dev); + + memory_region_init_io(&s->mmio, OBJECT(s), <pi_ops, s, + TYPE_ASPEED_LTPI, ASPEED_LTPI_NR_REGS); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio); +} + +static void ltpi_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + dc->realize = ltpi_realize; + dc->vmsd = &vmstate_ltpi; + device_class_set_legacy_reset(dc, ltpi_reset); +} + +static const TypeInfo ltpi_info = { + .name = TYPE_ASPEED_LTPI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(AspeedLTPIState), + .class_init = ltpi_class_init, +}; + +static void ltpi_register_types(void) +{ + type_register_static(<pi_info); +} + +type_init(ltpi_register_types); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index b1d8d8e5d2..45b16e7797 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -136,6 +136,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_hace.c', 'aspeed_i3c.c', 'aspeed_lpc.c', + 'aspeed_ltpi.c', 'aspeed_scu.c', 'aspeed_sbc.c', 'aspeed_sdmc.c', -- 2.43.0
