Solaris 8 appears to have a bug whereby it executes v9 MEMBAR instructions when booting a freshly installed image. According to the SPARC v8 architecture manual, whilst bits 14 and bits 13-0 of the "Read State Register Instructions" are notionally zero, they are marked as unused (i.e. ignored). In effect the v9 MEMBAR instruction becomes a v8 STBAR instruction on a 32-bit SPARC CPU.
Adjust the avail_32() logic in trans_MEMBAR() so that if a v9 MEMBAR instruction is executed on 32-bit SPARC, the equivalent of a v8 STBAR instruction is executed instead. Signed-off-by: Mark Cave-Ayland <[email protected]> Fixes: af25071c1d ("target/sparc: Move RDASR, STBAR, MEMBAR to decodetree") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3097 Reviewed-by: Richard Henderson <[email protected]> --- target/sparc/translate.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) v2: - Call trans_STBAR() directly instead of inlining it - Add R-B tag from Richard diff --git a/target/sparc/translate.c b/target/sparc/translate.c index b922e53bf1..735f5aae06 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2832,7 +2832,14 @@ static bool trans_STBAR(DisasContext *dc, arg_STBAR *a) static bool trans_MEMBAR(DisasContext *dc, arg_MEMBAR *a) { if (avail_32(dc)) { - return false; + /* + * At least Solaris 8 executes v9 MEMBAR instructions such as + * 0x8143e008 during boot. According to the SPARC v8 architecture + * manual, bits 13 and 12-0 are unused (notionally zero) so in + * this case if we assume the unused bits are not decoded then + * the instruction becomes 0x8143c000, or the equivalent of STBAR. + */ + return trans_STBAR(dc, NULL); } if (a->mmask) { /* Note TCG_MO_* was modeled on sparc64, so mmask matches. */ -- 2.39.5
