Hi all, Thanks Nick for the review. In patch v7:
1. Standardize the subject line of patch 1 and remove the trailing period. 2. Split into sub-functions to improve the patch's code readability and facilitate review. 3. Use more faster TCG ops, use tcg_gen_andi_tl() instead of tcg_gen_rem_tl(). 4. Add a tested-by signature for patch 2, as Eric has already tested it. History of changes: patch v6: - If a strided vector memory access instruction has non-zero vstart, check it through vlse/vsse helpers function. - Adjust the tcg test Makefile. https://lore.kernel.org/qemu-devel/[email protected]/ Patch v5: - Removed the redundant call to mark_vs_dirty(s) within the gen_ldst_stride_main_loop() function. https://lore.kernel.org/qemu-riscv/[email protected]/ Patch v4: - Use ctz32() replace to for-loop https://lore.kernel.org/qemu-devel/[email protected]/ Patch v3: - Fix the get_log2() function: https://lore.kernel.org/qemu-riscv/[email protected]/T/#t - Add test for vlsseg8e32 instruction. - Rebase on top of the latest master. Patch v2: - Split the TCG node emulation of the complex strided load/store operation into two separate functions to simplify the implementation: https://lore.kernel.org/qemu-riscv/[email protected]/ Patch v1: - Paolo submitted the initial version of the patch. https://lore.kernel.org/qemu-devel/[email protected]/ Tanks, Chao Chao Liu (2): target/riscv: Use tcg nodes for strided vector ld/st generation tests/tcg/riscv64: Add test for vlsseg8e32 instruction target/riscv/insn_trans/trans_rvv.c.inc | 348 ++++++++++++++++++++-- tests/tcg/riscv64/Makefile.softmmu-target | 7 +- tests/tcg/riscv64/test-vlsseg8e32.S | 107 +++++++ 3 files changed, 444 insertions(+), 18 deletions(-) create mode 100644 tests/tcg/riscv64/test-vlsseg8e32.S -- 2.50.1
