On 8. 8. 25. 18:07, Philippe Mathieu-Daudé wrote: > CAUTION: This email originated from outside of the organization. Do > not click links or open attachments unless you recognize the sender > and know the content is safe. > > > On 8/8/25 18:00, Philippe Mathieu-Daudé wrote: >> On 17/7/25 11:38, Djordje Todorovic wrote: >>> Add RISC-V implementation of the Coherent Manager Global Control >>> Register (CMGCR) device. It is based on the existing MIPS CMGCR >>> implementation but adapted for RISC-V systems. >>> >>> The CMGCR device provides global system control for multi-core >>> configurations in RISC-V systems. >>> >>> This is needed for the MIPS BOSTON AIA board. >>> >>> Signed-off-by: Chao-ying Fu <[email protected]> >>> Signed-off-by: Djordje Todorovic <[email protected]> >>> --- >>> hw/misc/Kconfig | 10 ++ >>> hw/misc/meson.build | 2 + >>> hw/misc/riscv_cmgcr.c | 234 >>> ++++++++++++++++++++++++++++++++++ >>> include/hw/misc/riscv_cmgcr.h | 49 +++++++ >>> 4 files changed, 295 insertions(+) >>> create mode 100644 hw/misc/riscv_cmgcr.c >>> create mode 100644 include/hw/misc/riscv_cmgcr.h >> >> >>> +static void riscv_gcr_realize(DeviceState *dev, Error **errp) >>> +{ >>> + RISCVGCRState *s = RISCV_GCR(dev); >> >> Please report an error for invalid num_vps values (0 or >MAX). > > Per the next patch: > > #define VPS_MAX 64 > > Is it possible to have a config with 7, 24 or 35 vps? > 64 is maximum, and we can have fewer than 64 vps. So, yes, it is possible to have that configuration.
>> >>> + >>> + /* Create local set of registers for each VP */ >>> + s->vps = g_new(RISCVGCRVPState, s->num_vps); >>> +} >
