Hi Philippe, We have considered implementing it as one module, but there
are changes between MIPS and RISC-V implementations that make that very hard. For example, the reset base for CPC is automatically set up for p8700. I have addressed your comments regarding v6, and I am preparing v7 for sending. Thanks, Djordje On 8. 8. 25. 18:42, Philippe Mathieu-Daudé wrote: > CAUTION: This email originated from outside of the organization. Do > not click links or open attachments unless you recognize the sender > and know the content is safe. > > > Hi, > > On 17/7/25 11:38, Djordje Todorovic wrote: >> I addressed several comments in this version, major ones: >> - split CPC / CMGCR into separated changes >> - split CPS into a separated change >> - added functional tests for boston-aia board >> >> Djordje Todorovic (14): > >> hw/misc: Add RISC-V CMGCR device implementation >> hw/misc: Add RISC-V CPC device implementation >> hw/riscv: Add support for RISCV CPS > I'm not keen on having theses models duplicated with the > MIPS ones. Are the IPs really different? They are just > dealing with bit masks to stop/start VPs AFAICT. > > Could we model them with plain CPUState objects instead?
