Hi Cédric > Subject: Re: [SPAM] [PATCH v1 10/21] hw/arm/ast27x0: Move DRAM and > SDMC initialization earlier to support memory aliasing > > On 7/17/25 05:40, Jamin Lin wrote: > > To support DRAM aliasing for coprocessors (SSP/TSP), this commit moves > > the initialization of the SDMC (SDRAM controller) and DRAM models > > earlier in the device realization order. > > > > In the upcoming changes, the PSP will expose a portion of its DRAM as > > shared memory by creating a memory region alias at a specific offset. > > This alias is mapped into the coprocessor's SDRAM address space, > > allowing both PSP and the coprocessor (SSP/TSP) to access the same > > physical memory through their respective views — PSP via its DRAM, and the > coprocessor via its SDRAM. > > > > The remapping is configured through SCU registers and enables shared > > memory communication between PSP and the coprocessors. > > > > Therefore, the DRAM and SDMC devices must be realized before: > > - the SCU, which configures the alias offset and size > > - the coprocessors, which access the alias through their SDRAM > > window > > > > No functional change. > > Please move this patch at the beginning of the series. It can be merged early. > Will do
Thanks for your review and suggestion. Jamin > > Thanks, > > C. > > > > > > Signed-off-by: Jamin Lin <[email protected]> > > --- > > hw/arm/aspeed_ast27x0.c | 40 ++++++++++++++++++++-------------------- > > 1 file changed, 20 insertions(+), 20 deletions(-) > > > > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index > > 2d27eb1deb..9d67c5f631 100644 > > --- a/hw/arm/aspeed_ast27x0.c > > +++ b/hw/arm/aspeed_ast27x0.c > > @@ -765,6 +765,26 @@ static void > aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) > > > qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i)); > > } > > > > + /* > > + * SDMC - SDRAM Memory Controller > > + * The SDMC controller is unlocked at SPL stage. > > + * At present, only supports to emulate booting > > + * start from u-boot stage. Set SDMC controller > > + * unlocked by default. It is a temporarily solution. > > + */ > > + object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, > > + &error_abort); > > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { > > + return; > > + } > > + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, > > + sc->memmap[ASPEED_DEV_SDMC]); > > + > > + /* RAM */ > > + if (!aspeed_soc_ast2700_dram_init(dev, errp)) { > > + return; > > + } > > + > > /* SRAM */ > > name = g_strdup_printf("aspeed.sram.%d", > CPU(&a->cpu[0])->cpu_index); > > if (!memory_region_init_ram(&s->sram, OBJECT(s), name, > > sc->sram_size, @@ -872,26 +892,6 @@ static void > aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) > > aspeed_soc_get_irq(s, > ASPEED_DEV_EHCI1 + i)); > > } > > > > - /* > > - * SDMC - SDRAM Memory Controller > > - * The SDMC controller is unlocked at SPL stage. > > - * At present, only supports to emulate booting > > - * start from u-boot stage. Set SDMC controller > > - * unlocked by default. It is a temporarily solution. > > - */ > > - object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, > > - &error_abort); > > - if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { > > - return; > > - } > > - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, > > - sc->memmap[ASPEED_DEV_SDMC]); > > - > > - /* RAM */ > > - if (!aspeed_soc_ast2700_dram_init(dev, errp)) { > > - return; > > - } > > - > > /* Net */ > > for (i = 0; i < sc->macs_num; i++) { > > object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", > > true,
