This patch set belongs to a list of series that add SVM support for VT-d.
Here, we focus on implementing the PRI API exposed through the PCIIOMMUOps.
This work is based on the VT-d specification version 4.1 (March 2023).
What is PRI?
''''''''''''
PRI (Page Request Interface) is a PCIe-level protocol that enables PCIe devices
to request page fault resolutions to the kernel through an IOMMU. PRI combined
with ATS are the 2 cornerstones of a technology called SVM (Shared Virtual
Memory) or SVA (Shared Virtual Addressing) which allows PCIe devices to read
from and write to the memory of userspace applications without requiring page
pinning.
Resources
'''''''''
Here is a link to our GitHub repository where you can find:
- Qemu with all the patches for SVM
- ATS
- PRI
- Device IOTLB invalidations
- Requests with already pre-translated addresses
- A demo device
- A simple driver for the demo device
- A userspace program (for testing and demonstration purposes)
https://github.com/BullSequana/Qemu-in-guest-SVM-demo
Clement Mathieu--Drif (5):
pcie: Add a way to get the outstanding page request allocation (pri)
from the config space.
intel_iommu: Bypass barrier wait descriptor
intel_iommu: Declare PRI constants and structures
intel_iommu: Declare registers for PRI
intel_iommu: Add PRI operations support
hw/i386/intel_iommu.c | 337 ++++++++++++++++++++++++++++++++-
hw/i386/intel_iommu_internal.h | 51 +++++
hw/pci/pcie.c | 8 +
include/hw/i386/intel_iommu.h | 1 +
include/hw/pci/pcie.h | 1 +
5 files changed, 397 insertions(+), 1 deletion(-)
--
2.51.0
