On Sat, Aug 30, 2025 at 12:11 AM Richard Henderson
<[email protected]> wrote:
> > (b) cpu_exit(): store-release cpu->exit_request, or
> > (b) cpu_interrupt(): store-release cpu->interrupt_request
>
> Mm. This is the reason we want the seq_cst of the qatomic_or.
> Perhaps comments in patch 7 should be expanded to document this?
Not entirely. There are cases in which a relaxed RMW atomic would
also work, for example this one in the CPU thread:
if (ctl_has_irq(env)) {
cpu_set_interrupt(cs, CPU_INTERRUPT_VIRQ);
}
and there are cases in which store-release is needed but atomicity
isn't (the ones under the BQL). It's putting the two requirements
together that requires patch 7.
And to be honest I am not sure there are other cases than the one
above, where cpu_set_interrupt()/cpu_reset_interrupt() is called
outside the BQL. But it's really a matter of time. Sooner or later
someone will move the APIC or GIC under its own lock, therefore we
might as well keep things clean already. "Written only under lock X"
is handy but I prefer to use it with moderation - like it's okay if
it's a primitive but not if there are dozens of calls across the code
base.
Thanks for the speedy review!
Paolo
