Signed-off-by: Manos Pitsidianakis <[email protected]>
---
gdb-xml/aarch64-core.xml | 5 +++++
target/arm/cpu.h | 1 +
target/arm/gdbstub64.c | 6 ++++++
3 files changed, 12 insertions(+)
diff --git a/gdb-xml/aarch64-core.xml b/gdb-xml/aarch64-core.xml
index
b8046510b9a085d30463d37b3ecc8d435f5fb7a4..19ad743dc5607b4021fb795bfb9b8e9cf0adef68
100644
--- a/gdb-xml/aarch64-core.xml
+++ b/gdb-xml/aarch64-core.xml
@@ -91,4 +91,9 @@
</flags>
<reg name="cpsr" bitsize="32" type="cpsr_flags"/>
+ <flags id="current_el_flags" size="8">
+ <!-- Exception Level. -->
+ <field name="EL" start="2" end="3"/>
+ </flags>
+ <reg name="CurrentEL" bitsize="64" type="current_el"/>
</feature>
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index
dc9b6dce4c92297b2636d0d7c0dce580f1806d5b..c3070cd9863381fac40f5640e0a7a84dfa1c6e06
100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1473,6 +1473,7 @@ void pmu_init(ARMCPU *cpu);
* AArch32 mode SPSRs are basically CPSR-format.
*/
#define PSTATE_SP (1U)
+#define PSTATE_EL (3U << 2)
#define PSTATE_M (0xFU)
#define PSTATE_nRW (1U << 4)
#define PSTATE_F (1U << 6)
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index
08e28585396816ab90d6d8e460ff8171892fe8da..16b564e1a970cb5e854a705619f71ffc61545a73
100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -48,6 +48,9 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray
*mem_buf, int n)
return gdb_get_reg64(mem_buf, env->pc);
case 33:
return gdb_get_reg32(mem_buf, pstate_read(env));
+ case 34:
+ /* CurrentEL */
+ return gdb_get_reg64(mem_buf, env->pstate & PSTATE_EL);
}
/* Unknown register. */
return 0;
@@ -77,6 +80,9 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t
*mem_buf, int n)
/* CPSR */
pstate_write(env, tmp);
return 4;
+ case 34:
+ /* CurrentEL */
+ return 0;
}
/* Unknown register. */
return 0;
--
2.47.2
