From: Alistair Francis <[email protected]>

The following changes since commit 9b80226ece693197af8a981b424391b68b5bc38e:

  Update version for the v10.1.0-rc1 release (2025-07-29 13:00:41 -0400)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20250730-2

for you to fetch changes up to 86bc3a0abf10072081cddd8dff25aa72c60e67b8:

  target/riscv: Restrict midelegh access to S-mode harts (2025-07-30 10:59:26 
+1000)

----------------------------------------------------------------
Third RISC-V PR for 10.1

* Fix pmp range wraparound on zero
* Update FADT and MADT versions in ACPI tables
* Fix target register read when source is inactive
* Add riscv_hwprobe entry to linux-user strace list
* Do not call GETPC() in check_ret_from_m_mode()
* Revert "Generate strided vector loads/stores with tcg nodes."
* Fix exception type when VU accesses supervisor CSRs
* Restrict mideleg/medeleg/medelegh access to S-mode harts
* Restrict midelegh access to S-mode harts

----------------------------------------------------------------
Daniel Henrique Barboza (3):
      linux-user/strace.list: add riscv_hwprobe entry
      target/riscv: do not call GETPC() in check_ret_from_m_mode()
      riscv: Revert "Generate strided vector loads/stores with tcg nodes."

Jay Chang (2):
      target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts
      target/riscv: Restrict midelegh access to S-mode harts

Sunil V L (3):
      bios-tables-test-allowed-diff.h: Allow RISC-V FADT and MADT changes
      hw/riscv/virt-acpi-build.c: Update FADT and MADT versions
      tests/data/acpi/riscv64: Update expected FADT and MADT

Vac Chen (1):
      target/riscv: Fix pmp range wraparound on zero

Xu Lu (1):
      target/riscv: Fix exception type when VU accesses supervisor CSRs

Yang Jialong (1):
      intc/riscv_aplic: Fix target register read when source is inactive

 hw/intc/riscv_aplic.c                   |   6 +-
 hw/riscv/virt-acpi-build.c              |  25 +--
 target/riscv/csr.c                      |  15 +-
 target/riscv/op_helper.c                |  15 +-
 target/riscv/pmp.c                      |   7 +-
 target/riscv/insn_trans/trans_rvv.c.inc | 323 +++++---------------------------
 linux-user/strace.list                  |   3 +
 tests/data/acpi/riscv64/virt/APIC       | Bin 116 -> 116 bytes
 tests/data/acpi/riscv64/virt/FACP       | Bin 276 -> 276 bytes
 9 files changed, 90 insertions(+), 304 deletions(-)

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