On 3/7/25 12:49, Djordje Todorovic wrote:
The board model supports up to 64 harts with MIPS CPS, MIPS GCR,
MIPS CPC, AIA plic, and AIA clint devices. The model can create
boot code, if there is no -bios parameter. We can specify -smp x,
cores=y,thread=z.
Ex: Use 4 cores and 2 threads with each core to
have 8 smp cpus as follows.
qemu-system-riscv64 -cpu mips-p8700 \
-m 2G -M boston-aia \
-smp 8,cores=4,threads=2 -kernel fw_payload.bin \
-drive file=rootfs.ext2,format=raw -serial stdio
Signed-off-by: Chao-ying Fu <c...@mips.com>
Signed-off-by: Djordje Todorovic <djordje.todoro...@htecgroup.com>
---
configs/devices/riscv64-softmmu/default.mak | 1 +
docs/system/riscv/mips.rst | 25 +
docs/system/target-riscv.rst | 1 +
hw/riscv/Kconfig | 6 +
hw/riscv/boston-aia.c | 484 ++++++++++++++++++++
hw/riscv/cps.c | 187 ++++++++
hw/riscv/meson.build | 1 +
include/hw/riscv/cps.h | 75 +++
8 files changed, 780 insertions(+)
Patch is too big. Please provide the CPS as a preliminary patch,
then the Boston AIA board, then add tests for this new board. You
can find various examples in the tests/functional/ directory.
Regards,
Phil.
