Re: [PATCH v5 05/11] target/loongarch: add msg interrupt CSR registers

[Bibo Mao]

On 2025/7/11 下午4:59, Song Gao wrote:

include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.

Signed-off-by: Song Gao <gaos...@loongson.cn>
---
  target/loongarch/cpu-csr.h |  3 +++
  target/loongarch/cpu.h     | 10 ++++++++++
  target/loongarch/machine.c | 27 +++++++++++++++++++++++++--
  3 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index 0834e91f30..4792677086 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -186,6 +186,9 @@ FIELD(CSR_MERRCTL, ISMERR, 0, 1)

#define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */ +#define LOONGARCH_CSR_MSGIS(N) (0xa0 + N)

+#define LOONGARCH_CSR_MSGIR               0xa4
+
  /* Direct map windows CSRs*/
  #define LOONGARCH_CSR_DMW(N)         (0x180 + N)
  FIELD(CSR_DMW, PLV0, 0, 1)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 56fc4a1459..208d3e0cd3 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -233,6 +233,12 @@ FIELD(TLB_MISC, ASID, 1, 10)
  FIELD(TLB_MISC, VPPN, 13, 35)
  FIELD(TLB_MISC, PS, 48, 6)

+/*Msg interrupt registers */

+FIELD(CSR_MSGIS, IS, 0, 63)
+FIELD(CSR_MSGIR, INTNUM, 0, 8)
+FIELD(CSR_MSGIR, ACTIVE, 31, 1)
+FIELD(CSR_MSGIE, PT, 0, 8)
+
  #define LSX_LEN    (128)
  #define LASX_LEN   (256)

@@ -350,6 +356,10 @@ typedef struct CPUArchState {

      uint64_t CSR_DBG;
      uint64_t CSR_DERA;
      uint64_t CSR_DSAVE;
+    /* Msg interrupt registers */
+    uint64_t CSR_MSGIS[4];

It will better if there is macro replaced with 4.

+    uint64_t CSR_MSGIR;
+    uint64_t CSR_MSGIE;
      struct {
          uint64_t guest_addr;
      } stealtime;
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
index 4e70f5c879..9eddb9341a 100644
--- a/target/loongarch/machine.c
+++ b/target/loongarch/machine.c
@@ -10,6 +10,7 @@
  #include "migration/cpu.h"
  #include "system/tcg.h"
  #include "vec.h"
+#include "hw/loongarch/virt.h"

static const VMStateDescription vmstate_fpu_reg = {

      .name = "fpu_reg",
@@ -45,6 +46,27 @@ static const VMStateDescription vmstate_fpu = {
      },
  };

+static bool msg_needed(void *opaque)

+{
+    MachineState *ms = MACHINE(qdev_get_machine());
+    LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(ms);
+
+    return !!(lvms->misc_feature & BIT(IOCSRF_AVEC));

how about use virt_has_avecintc() like this?
   return virt_has_avecintc(lvms);

+}
+
+static const VMStateDescription vmstate_msg = {
+    .name = "cpu/msg",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = msg_needed,
+    .fields = (const VMStateField[]) {
+        VMSTATE_UINT64_ARRAY(env.CSR_MSGIS, LoongArchCPU, 4),

ditto, it will be better if there is macro replaced with 4.

Regards
Bibo Mao

+        VMSTATE_UINT64(env.CSR_MSGIR, LoongArchCPU),
+        VMSTATE_UINT64(env.CSR_MSGIE, LoongArchCPU),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
  static const VMStateDescription vmstate_lsxh_reg = {
      .name = "lsxh_reg",
      .version_id = 1,
@@ -168,8 +190,8 @@ static const VMStateDescription vmstate_tlb = {
  /* LoongArch CPU state */
  const VMStateDescription vmstate_loongarch_cpu = {
      .name = "cpu",
-    .version_id = 3,
-    .minimum_version_id = 3,
+    .version_id = 4,
+    .minimum_version_id = 4,
      .fields = (const VMStateField[]) {
          VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
          VMSTATE_UINTTL(env.pc, LoongArchCPU),
@@ -245,6 +267,7 @@ const VMStateDescription vmstate_loongarch_cpu = {
          &vmstate_tlb,
  #endif
          &vmstate_lbt,
+        &vmstate_msg,
          NULL
      }
  };