On Mon, May 21, 2012 at 05:31:06PM -0500, Anthony Liguori wrote: > On 05/21/2012 05:26 PM, Benjamin Herrenschmidt wrote: > >On Mon, 2012-05-21 at 17:18 -0500, Anthony Liguori wrote: > >>But this isn't what this series is about. > >> > >>This series is only attempting to make sure that writes are ordered > >>with respect > >>to other writes in main memory. > > > >Actually, it applies to both reads and writes. They can't pass each > >other either and that can be fairly important. > > That's fine but that's a detail of the bus. > > >It's in fact the main contention point because if it was only writes we > >could just use wmb and be done with it (that's a nop on x86). > > > >Because we are trying to order everything (and specifically store > >followed by a load), we need a full barrier which is more expensive on > >x86. > > I think the thing to do is make the barrier implemented in the dma > API and allow it to be overridden by the bus. The default > implementation should be a full barrier.
I think what's called for is what Ben proposed: track last transaction and use the appropriate barrier. > If we can establish that the bus guarantees a weaker ordering > guarantee, a bus could override the default implementation and do > something weaker. > > Regards, > > Anthony Liguori OK. Just not another level of indirect function callbacks please. Make it a library so each bus can do the right thing. There are not so many buses. -- MST
