From: Ed Tanous <etan...@nvidia.com> Aspeed2600 has two spi lanes; Add a new struct that can mount the second SPI.
Signed-off-by: Ed Tanous <etan...@nvidia.com> Reviewed-by: Cédric Le Goater <c...@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-2-etan...@nvidia.com Signed-off-by: Cédric Le Goater <c...@redhat.com> --- include/hw/arm/aspeed.h | 2 ++ hw/arm/aspeed.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index 973277bea655..6c364556565a 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -35,7 +35,9 @@ struct AspeedMachineClass { uint32_t hw_strap2; const char *fmc_model; const char *spi_model; + const char *spi2_model; uint32_t num_cs; + uint32_t num_cs2; uint32_t macs_mask; void (*i2c_init)(AspeedMachineState *bmc); uint32_t uart_default; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 94897505f8e3..8d7757e11f1c 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -465,6 +465,8 @@ static void aspeed_machine_init(MachineState *machine) aspeed_board_init_flashes(&bmc->soc->spi[0], bmc->spi_model ? bmc->spi_model : amc->spi_model, 1, amc->num_cs); + aspeed_board_init_flashes(&bmc->soc->spi[1], + amc->spi2_model, 1, amc->num_cs2); } if (machine->kernel_filename && sc->num_cpus > 1) { -- 2.50.0
