On 6/20/2025 5:27 PM, Zhao Liu wrote:
> Based on legacy_l1d_cachei_amd, legacy_l1i_cache_amd, legacy_l2_cache_amd
> and legacy_l3_cache, build a complete legacy AMD cache model, which can
> clarify the purpose of these trivial legacy cache models, simplify the
> initialization of cache info in X86CPUState, and make it easier to
> handle compatibility later.
>
> Signed-off-by: Zhao Liu <zhao1....@intel.com>
> ---
> target/i386/cpu.c | 112 ++++++++++++++++++++++------------------------
> 1 file changed, 53 insertions(+), 59 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index ec229830c532..bf8d7a19c88d 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -643,60 +643,58 @@ static void encode_topo_cpuid8000001e(X86CPU *cpu,
> X86CPUTopoInfo *topo_info,
> * These are legacy cache values. If there is a need to change any
> * of these values please use builtin_x86_defs
> */
> -static CPUCacheInfo legacy_l1d_cache_amd = {
> - .type = DATA_CACHE,
> - .level = 1,
> - .size = 64 * KiB,
> - .self_init = 1,
> - .line_size = 64,
> - .associativity = 2,
> - .sets = 512,
> - .partitions = 1,
> - .lines_per_tag = 1,
> - .no_invd_sharing = true,
> - .share_level = CPU_TOPOLOGY_LEVEL_CORE,
> -};
> -
> -static CPUCacheInfo legacy_l1i_cache_amd = {
> - .type = INSTRUCTION_CACHE,
> - .level = 1,
> - .size = 64 * KiB,
> - .self_init = 1,
> - .line_size = 64,
> - .associativity = 2,
> - .sets = 512,
> - .partitions = 1,
> - .lines_per_tag = 1,
> - .no_invd_sharing = true,
> - .share_level = CPU_TOPOLOGY_LEVEL_CORE,
> -};
> -
> -static CPUCacheInfo legacy_l2_cache_amd = {
> - .type = UNIFIED_CACHE,
> - .level = 2,
> - .size = 512 * KiB,
> - .line_size = 64,
> - .lines_per_tag = 1,
> - .associativity = 16,
> - .sets = 512,
> - .partitions = 1,
> - .share_level = CPU_TOPOLOGY_LEVEL_CORE,
> -};
> -
> -/* Level 3 unified cache: */
> -static CPUCacheInfo legacy_l3_cache = {
> - .type = UNIFIED_CACHE,
> - .level = 3,
> - .size = 16 * MiB,
> - .line_size = 64,
> - .associativity = 16,
> - .sets = 16384,
> - .partitions = 1,
> - .lines_per_tag = 1,
> - .self_init = true,
> - .inclusive = true,
> - .complex_indexing = true,
> - .share_level = CPU_TOPOLOGY_LEVEL_DIE,
> +static const CPUCaches legacy_amd_cache_info = {
> + .l1d_cache = &(CPUCacheInfo) {
> + .type = DATA_CACHE,
> + .level = 1,
> + .size = 64 * KiB,
> + .self_init = 1,
> + .line_size = 64,
> + .associativity = 2,
> + .sets = 512,
> + .partitions = 1,
> + .lines_per_tag = 1,
> + .no_invd_sharing = true,
> + .share_level = CPU_TOPOLOGY_LEVEL_CORE,
> + },
> + .l1i_cache = &(CPUCacheInfo) {
> + .type = INSTRUCTION_CACHE,
> + .level = 1,
> + .size = 64 * KiB,
> + .self_init = 1,
> + .line_size = 64,
> + .associativity = 2,
> + .sets = 512,
> + .partitions = 1,
> + .lines_per_tag = 1,
> + .no_invd_sharing = true,
> + .share_level = CPU_TOPOLOGY_LEVEL_CORE,
> + },
> + .l2_cache = &(CPUCacheInfo) {
> + .type = UNIFIED_CACHE,
> + .level = 2,
> + .size = 512 * KiB,
> + .line_size = 64,
> + .lines_per_tag = 1,
> + .associativity = 16,
> + .sets = 512,
> + .partitions = 1,
> + .share_level = CPU_TOPOLOGY_LEVEL_CORE,
> + },
> + .l3_cache = &(CPUCacheInfo) {
> + .type = UNIFIED_CACHE,
> + .level = 3,
> + .size = 16 * MiB,
> + .line_size = 64,
> + .associativity = 16,
> + .sets = 16384,
> + .partitions = 1,
> + .lines_per_tag = 1,
> + .self_init = true,
> + .inclusive = true,
> + .complex_indexing = true,
> + .share_level = CPU_TOPOLOGY_LEVEL_DIE,
> + },
> };
>
> /*
> @@ -8982,11 +8980,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error
> **errp)
> }
>
> env->cache_info_cpuid4 = legacy_intel_cache_info;
> -
> - env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
> - env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
> - env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
> - env->cache_info_amd.l3_cache = &legacy_l3_cache;
> + env->cache_info_amd = legacy_amd_cache_info;
> }
>
> #ifndef CONFIG_USER_ONLY
Reviewed-by: Dapeng Mi <dapeng1...@linux.intel.com>
