> > + /* > > + * Newer Intel CPUs (having the cores without L3, e.g., Intel MTL, ARL) > > + * use CPUID 0x4 leaf to describe cache topology, by encoding CPUID 0x2 > > + * leaf with 0xFF. For older CPUs (without 0x4 leaf), it's also valid > > + * to just ignore l3's code if there's no l3. > > s/l3/L3/g
Sure! > Others look good to me. > > Reviewed-by: Dapeng Mi <dapeng1...@linux.intel.com> Thanks!
