On 6/23/25 11:42 AM, Shameer Kolothum wrote:
> For the legacy SMMUv3 test, the setup includes three PCIe Root Complexes,
> one of which has bypass_iommu enabled. The generated IORT table contains
> a single SMMUv3 node and a Root Complex node with three ID mappings. Two
> of these ID mappings have output references pointing to the SMMUv3 node
> and the remianing one points to ITS.
remaining
>
> For the -device arm-smmuv3,... test, the configuration also includes three
> Root Complexes, with two connected to separate SMMUv3 devices.
By the way I have never paid attention to the fact there is only 1
single IORT node despite we have 3 GPEX/PXB devices
> The resulting IORT table contains two SMMUv3 nodes and a Root Complex node
> with ID mappings of which two of the ID mappings have output references
above is a bit difficult to parse.
Suggesting:
The resulting IORT table contains 1 RC node, 2 SMMU nodes and 1 ITS node.
> pointing to two different SMMUv3 nodes and the remaining ones to ITS.
RC node features 3 ID mappings. 2 of them target the 2 SMMU nodes while
the last one targets the ITS.
a drawing might be simpler
pcie.0 -> {SMMU0} -> {ITS}
{RC} pcie.1 -> {SMMU1} -> {ITS}
pcie.2 -> {ITS}
>
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.th...@huawei.com>
> ---
> tests/qtest/bios-tables-test.c | 86 ++++++++++++++++++++++++++++++++++
> 1 file changed, 86 insertions(+)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index 0b2bdf9d0d..1c50541b43 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -2231,6 +2231,86 @@ static void test_acpi_aarch64_virt_viot(void)
> free_test_data(&data);
> }
>
> +static void test_acpi_aarch64_virt_smmuv3_legacy(void)
> +{
> + test_data data = {
> + .machine = "virt",
> + .arch = "aarch64",
> + .tcg_only = true,
> + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
> + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
> + .ram_start = 0x40000000ULL,
> + .scan_len = 128ULL * MiB,
> + };
> +
> + /*
> + * cdrom is plugged into scsi controller to avoid conflict
> + * with pxb-pcie. See comments in test_acpi_aarch64_virt_tcg_pxb() for
> + * details.
> + *
> + * The setup includes three PCIe root complexes, one of which has
> + * bypass_iommu enabled. The generated IORT table contains a single
> + * SMMUv3 node and a Root Complex node with three ID mappings. Two
> + * of the ID mappings have output references pointing to the SMMUv3
> + * node and the remaining one points to ITS.
> + */
> + data.variant = ".smmuv3-legacy";
> + test_acpi_one(" -device pcie-root-port,chassis=1,id=pci.1"
> + " -device virtio-scsi-pci,id=scsi0,bus=pci.1"
> + " -drive file="
> +
> "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2,"
> + "if=none,media=cdrom,id=drive-scsi0-0-0-1,readonly=on"
> + " -device scsi-cd,bus=scsi0.0,scsi-id=0,"
> + "drive=drive-scsi0-0-0-1,id=scsi0-0-0-1,bootindex=1"
> + " -cpu cortex-a57"
> + " -M iommu=smmuv3"
> + " -device pxb-pcie,id=pcie.1,bus=pcie.0,bus_nr=0x10"
> + " -device
> pxb-pcie,id=pcie.2,bus=pcie.0,bus_nr=0x20,bypass_iommu=on",
> + &data);
> + free_test_data(&data);
> +}
> +
> +static void test_acpi_aarch64_virt_smmuv3_dev(void)
> +{
> + test_data data = {
> + .machine = "virt",
> + .arch = "aarch64",
> + .tcg_only = true,
> + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
> + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
> + .ram_start = 0x40000000ULL,
> + .scan_len = 128ULL * MiB,
> + };
> +
> + /*
> + * cdrom is plugged into scsi controller to avoid conflict
> + * with pxb-pcie. See comments in test_acpi_aarch64_virt_tcg_pxb()
> + * for details.
> + *
> + * The setup includes three PCie root complexes, two of which are
> + * connected to separate SMMUv3 devices. The resulting IORT table
> + * contains two SMMUv3 nodes and a Root Complex node with ID mappings
> + * of which two of the ID mappings have output references pointing
> + * to two different SMMUv3 nodes and the remaining ones pointing to
> + * ITS.
> + */
> + data.variant = ".smmuv3-dev";
> + test_acpi_one(" -device pcie-root-port,chassis=1,id=pci.1"
> + " -device virtio-scsi-pci,id=scsi0,bus=pci.1"
> + " -drive file="
> +
> "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2,"
> + "if=none,media=cdrom,id=drive-scsi0-0-0-1,readonly=on"
> + " -device scsi-cd,bus=scsi0.0,scsi-id=0,"
> + "drive=drive-scsi0-0-0-1,id=scsi0-0-0-1,bootindex=1"
> + " -cpu cortex-a57"
> + " -device arm-smmuv3,primary-bus=pcie.0,id=smmuv3.0"
> + " -device pxb-pcie,id=pcie.1,bus=pcie.0,bus_nr=0x10"
> + " -device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1"
> + " -device pxb-pcie,id=pcie.2,bus=pcie.0,bus_nr=0x20",
> + &data);
> + free_test_data(&data);
> +}
> +
> #ifndef _WIN32
> # define DEV_NULL "/dev/null"
> #else
> @@ -2586,6 +2666,12 @@ int main(int argc, char *argv[])
> if (qtest_has_device("virtio-iommu-pci")) {
> qtest_add_func("acpi/virt/viot",
> test_acpi_aarch64_virt_viot);
> }
> + qtest_add_func("acpi/virt/smmuv3-legacy",
> + test_acpi_aarch64_virt_smmuv3_legacy);
> + if (qtest_has_device("arm-smmuv3")) {
> + qtest_add_func("acpi/virt/smmuv3-dev",
> + test_acpi_aarch64_virt_smmuv3_dev);
> + }
> }
> } else if (strcmp(arch, "riscv64") == 0) {
> if (has_tcg && qtest_has_device("virtio-blk-pci")) {
Besides
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Eric
