Hi Aleksandar,

On 25/6/25 22:10, Aleksandar Rakic wrote:
From: Aleksandar Rakic <aleksandar.ra...@htecgroup.com>

Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions.
Reuse zlib crc32() and Linux crc32c().

Enable CRC for mips64r6.

Signed-off-by: Yongbok Kim <yongbok....@mips.com>
Signed-off-by: Aleksandar Markovic <amarko...@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.ra...@htecgroup.com>
Reviewed-by: Aleksandar Rikalo <arik...@gmail.com>
---
  target/mips/cpu-defs.c.inc                    |  10 +-
  target/mips/helper.h                          |   2 +
  target/mips/meson.build                       |   1 +
  target/mips/tcg/op_helper.c                   |  27 ++++
  target/mips/tcg/translate.c                   |  37 +++++
  target/mips/tcg/translate.h                   |   1 +
  tests/tcg/mips/include/wrappers_mips64r6.h    |  35 +++++
  tests/tcg/mips/user/isa/mips64r6/crc/Makefile |  42 ++++++


  static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
  {
      int rs, rt, rd, sa;
@@ -13463,6 +13488,17 @@ static void decode_opc_special3_r6(CPUMIPSState *env, 
DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode);
      switch (op1) {
+    case OPC_CRC32:
+        if (unlikely(!ctx->crcp) ||
+            unlikely((extract32(ctx->opcode, 6, 2) == 3) &&
+                     (!(ctx->hflags & MIPS_HFLAG_64))) ||
+            unlikely((extract32(ctx->opcode, 8, 3) >= 2))) {
+            gen_reserved_instruction(ctx);
+        }
+        gen_crc32(ctx, rt, rs, rt,
+                  extract32(ctx->opcode, 6, 2),
+                  extract32(ctx->opcode, 8, 3));
+        break;

You missed my comment from v2:
https://lore.kernel.org/qemu-devel/a79706ef-9c53-4fb8-857c-e49475a55...@linaro.org/

The decodetree change should look like:

-- >8 --
diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode
index d6989cf56e8..5074338aa57 100644
--- a/target/mips/tcg/rel6.decode
+++ b/target/mips/tcg/rel6.decode
@@ -16,11 +16,16 @@

 &r                  rs rt rd sa

+&special3_crc       rs rt c sz
+
 @lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &r
+@crc32              ...... rs:5 rt:5 ..... c:3 sz:2 ......   &special3_crc

 LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
 DLSA                000000 ..... ..... ..... 000 .. 010101  @lsa

+CRC32               011111 ..... ..... 00000 ... .. 001111  @crc32
+
 REMOVED             010011 ----- ----- ----- ----- ------   # COP1X (COP3)

 REMOVED             011100 ----- ----- ----- ----- ------   # SPECIAL2
---

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