On Fri, Jun 13, 2025 at 1:58 PM Peter Maydell <[email protected]> wrote: > > On Mon, 26 May 2025 at 09:55, Clément Chigot <[email protected]> wrote: > > > > This series enhances Xilinx ZynqMP support to allow booting on RPUs and > > ease gdb connections to them. > > > > It was validated with home-made binaries. FreeRTOS was tested but without > > success: outputs/IRQ seems broken. AFAICT, FreeRTOS is expecting Xilinx's > > QEMU thus I didn't investigate further, but I'd still like advice > > on the 3rd patch ("wire a second GIC") since it could be related to it. > > > > Changes since v1: > > - add doc for "first-cpu-index" new property in arm_gic.h. > > > > Clément Chigot (2): > > hw/arm: make cpu targeted by arm_load_kernel the primary CPU. > > hw/arm/xlnx-zynqmp: adapt cluster-id based on the boot cpu > > > > Frederic Konrad (2): > > hw/intc/arm_gic: introduce a first-cpu-index property > > hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5 > > Hi; I've taken the first 2 patches in this series into > target-arm.next. I left some review comments on patch 3.
Thanks a lot. I've just sent a v3 addressing them. > For patch 4, I still feel this is something that should > be dealt with at the gdb end (e.g. gdb should support > "connect to this target and connect to remote-inferior 2, > not inferior 1, and don't fall over just because you > don't know the architecture of inferior 1"). Yeah, I'm totally fine with that, I've removed it from v3. PS: I'll be off for a few weeks but should be able to make a v4 if needed before 10.1 soft freeze. Thanks, Clément
