Thanks for Alistair Francis's reply, and now this version has changed as follows: 1. Rebase to https://github.com/alistair23/qemu/tree/riscv-to- apply.next. 2. The Review-by information has been added.
lxx (1): target/riscv: Add Zilsd and Zclsd extension support target/riscv/cpu.c | 4 + target/riscv/cpu_cfg_fields.h.inc | 2 + target/riscv/insn16.decode | 8 ++ target/riscv/insn32.decode | 12 ++- target/riscv/insn_trans/trans_zilsd.c.inc | 112 ++++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 30 ++++++ target/riscv/translate.c | 1 + 7 files changed, 167 insertions(+), 2 deletions(-) create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc -- 2.45.3
