Hi Peter, On 6/9/25 12:41 PM, Peter Maydell wrote: > Currently we define the ID_AA64PFR2_EL1 encoding as reserved (with > the required RAZ behaviour for unassigned system registers in the ID > register encoding space). Newer architecture versions start to > define fields in this ID register, so define the appropriate > constants and implement it as an ID register backed by a field in > cpu->isar. Since none of our CPUs set that isar field to non-zero, > there is no behavioural change here (other than the name exposed to > the user via the gdbstub), but this paves the way for implementing > the new features that use fields in this register. > > The fields here are the ones documented in rev L.a of the Arm ARM.
this conflicts with [PATCH v7 00/14] arm: rework id register storage <https://lore.kernel.org/all/87ikl99oxg....@redhat.com/#r> on which Connie recently pinged and which sounded mostly ready, except of course if you have objections. Thanks Eric > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/arm/cpu-features.h | 5 +++++ > target/arm/cpu.h | 1 + > target/arm/helper.c | 6 ++++-- > target/arm/hvf/hvf.c | 2 ++ > target/arm/kvm.c | 2 ++ > 5 files changed, 14 insertions(+), 2 deletions(-) > > diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h > index db80ea1cc67..a8a94ee9d96 100644 > --- a/target/arm/cpu-features.h > +++ b/target/arm/cpu-features.h > @@ -275,6 +275,11 @@ FIELD(ID_AA64PFR1, MTEX, 52, 4) > FIELD(ID_AA64PFR1, DF2, 56, 4) > FIELD(ID_AA64PFR1, PFAR, 60, 4) > > +FIELD(ID_AA64PFR2, MTEPERM, 0, 4) > +FIELD(ID_AA64PFR2, MTESTOREONLY, 4, 4) > +FIELD(ID_AA64PFR2, MTEFAR, 8, 4) > +FIELD(ID_AA64PFR2, FPMR, 32, 4) > + > FIELD(ID_AA64MMFR0, PARANGE, 0, 4) > FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) > FIELD(ID_AA64MMFR0, BIGEND, 8, 4) > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 9364d221744..93e055e34fd 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1031,6 +1031,7 @@ struct ArchCPU { > uint64_t id_aa64isar2; > uint64_t id_aa64pfr0; > uint64_t id_aa64pfr1; > + uint64_t id_aa64pfr2; > uint64_t id_aa64mmfr0; > uint64_t id_aa64mmfr1; > uint64_t id_aa64mmfr2; > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 76312102879..31b667b7e05 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -7927,11 +7927,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) > .access = PL1_R, .type = ARM_CP_CONST, > .accessfn = access_aa64_tid3, > .resetvalue = cpu->isar.id_aa64pfr1}, > - { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, > + { .name = "ID_AA64PFR2_EL1", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, > .access = PL1_R, .type = ARM_CP_CONST, > .accessfn = access_aa64_tid3, > - .resetvalue = 0 }, > + .resetvalue = cpu->isar.id_aa64pfr2 }, > { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, > .access = PL1_R, .type = ARM_CP_CONST, > @@ -8179,6 +8179,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) > R_ID_AA64PFR1_SSBS_MASK | > R_ID_AA64PFR1_MTE_MASK | > R_ID_AA64PFR1_SME_MASK }, > + { .name = "ID_AA64PFR2_EL1", > + .exported_bits = 0 }, > { .name = "ID_AA64PFR*_EL1_RESERVED", > .is_glob = true }, > { .name = "ID_AA64ZFR0_EL1", > diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c > index 42258cc2d88..b4f2b743901 100644 > --- a/target/arm/hvf/hvf.c > +++ b/target/arm/hvf/hvf.c > @@ -493,6 +493,7 @@ static struct hvf_sreg_match hvf_sreg_match[] = { > { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) }, > #endif > { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 1) }, > + /* Add ID_AA64PFR2_EL1 here when HVF supports it */ > { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) }, > { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) }, > { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) }, > @@ -864,6 +865,7 @@ static bool > hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) > } regs[] = { > { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 }, > { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, > + /* Add ID_AA64PFR2_EL1 here when HVF supports it */ > { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, > { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, > { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, > diff --git a/target/arm/kvm.c b/target/arm/kvm.c > index 74fda8b8090..915fc04e54e 100644 > --- a/target/arm/kvm.c > +++ b/target/arm/kvm.c > @@ -292,6 +292,8 @@ static bool > kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) > } else { > err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, > ARM64_SYS_REG(3, 0, 0, 4, 1)); > + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr2, > + ARM64_SYS_REG(3, 0, 0, 4, 2)); > err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, > ARM64_SYS_REG(3, 0, 0, 4, 5)); > err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0,
