Use the IOCSRF_AVEC bit for avdance interrupt controller drivers avecintc_enable[1] and set the default value of the MISC_FUNC_REG bit IOCSRM_AVEC_EN. and set the default value of the MISC_FUNC_REG bit IOCSRM_AVEC_EN.
[1]:https://github.com/torvalds/linux/blob/master/drivers/irqchip/irq-loongarch-avec.c Signed-off-by: Song Gao <gaos...@loongson.cn> --- hw/loongarch/virt.c | 4 ++++ target/loongarch/cpu.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 1b504047db..90d4643721 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -548,6 +548,8 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr, break; case FEATURE_REG: ret = BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); + /*TODO: check bit IOCSRF_AVEC with virt_is_avec_enabled */ + ret |= BIT(IOCSRF_AVEC); if (kvm_enabled()) { ret |= BIT(IOCSRF_VM); } @@ -573,6 +575,8 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, hwaddr addr, if (features & BIT(EXTIOI_ENABLE_INT_ENCODE)) { ret |= BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE); } + /* enable avec default */ + ret |= BIT_ULL(IOCSRM_AVEC_EN); break; default: g_assert_not_reached(); diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 262bf87f7b..7cceec1204 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -31,6 +31,7 @@ #define IOCSRF_DVFSV1 7 #define IOCSRF_GMOD 9 #define IOCSRF_VM 11 +#define IOCSRF_AVEC 15 #define VERSION_REG 0x0 #define FEATURE_REG 0x8 @@ -39,6 +40,7 @@ #define MISC_FUNC_REG 0x420 #define IOCSRM_EXTIOI_EN 48 #define IOCSRM_EXTIOI_INT_ENCODE 49 +#define IOCSRM_AVEC_EN 51 #define IOCSR_MEM_SIZE 0x428 -- 2.34.1
